# US 11,907,546 B2 · Memory system and operations of the same

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- Number: US 11,907,546 B2
- Document ID: US11907546B2
- Status: Granted
- Kind: B2
- Application number: 17/894,752
- Filed: 2022-08-24
- Published: 2023-02-23
- Granted: 2024-02-20
- Earliest claimed: 2019-01-15
- Applicants: Lodestar Licensing Group LLC
- Inventors: Dean D. Gans
- Web page: https://patentgrep.com/patent/US11907546B2

## CPC

- G06F 3/0622: {in relation to access}
- H04B 14/023: {using pulse amplitude modulation}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0646: {Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems}
- G06F 3/0673: {Single storage device}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04B: TRANSMISSION
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

## Claims

### Claim 1

An apparatus, comprising:
a first array of memory cells configured for access operations;
a first interface for communicating first data with a host device, wherein the first interface is configured to support a first modulation scheme using a first quantity of voltage levels;
a second interface for communicating second data with a memory die, the memory die comprising a second array of memory cells configured for access operations, wherein the second interface comprises a set of buffers configured to store the second data transferred between the memory die and the first array of memory cells, and wherein the second interface is configured to support a second modulation scheme using a second Quantity of voltage levels that is different than the first Quantity of voltage levels; and
a third interface configured for communicating control information with a controller that is coupled with the apparatus and the memory die.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein:
the first interface is configured to support a multi-symbol modulation scheme selected from PAM3, PAM4, PAM5, PAM6, PAM7, PAM8, PAM2y (y>3), quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK); and
the second interface is configured to support a binary symbol modulation scheme selected from NRZ encoding, unipolar encoding, bipolar encoding, Manchester encoding, and PAM2 encoding.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
the first interface is configured for coupling with a first set of data channels associated with a first rate of data transfer; and
the second interface is configured for coupling with a second set of data channels associated with a second rate of data transfer that is lower than the first rate of data transfer.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the first array of memory cells is associated with first density of memory cells that is less than a second density of memory cells of the second array of memory cells.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the third interface is configured for receiving, from the controller, command and address information associated with a set of data; and
the first interface is configured for transmitting, to the host device and based at least in part on the command and address information, the set of data.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein access lines of the first array of memory cells are associated with a first length that is shorter than a second length associated with access lines of the second array of memory cells.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the first interface is operable to support a first operation mode associated with a first burst length and a second operation mode associated with a second burst length that is greater than the first burst length.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein a quantity of memory cells of the first array of memory cells is less than a quantity of memory cells of the second array of memory cells.

### Claim 9

A method, comprising:
receiving, at a first memory device via a first interface, a first set of signals comprising data from a second memory device, the first set of signals modulated according to a first modulation scheme using a first quantity of voltage levels, wherein the first interface comprises a set of buffers for storing the data, wherein the first memory device is configured for access operations with a first array of memory cells and the second memory device is configured for access operations with a second array of memory cells;
storing the data at the first memory device based at least in part on receiving the first set of signals; and
transmitting, to a host device via a second interface, a second set of signals comprising the data based at least in part on receiving the data, the second set of signals modulated according to a second modulation scheme using a second quantity of voltage levels that is different than the first quantity of voltage levels, wherein the set of buffers is configured to support concurrent data management between the first memory device and the second memory device.

### Claim 10 (depends on 9)

The method of claim 9, wherein:
the first modulation scheme is a binary symbol modulation scheme selected from NRZ encoding, unipolar encoding, bipolar encoding, Manchester encoding, and PAM2 encoding; and
the second modulation scheme is a multi-symbol modulation scheme selected from PAM3, PAM4, PAM5, PAM6, PAM7, PAM8, PAM2y (y>3), quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK).

### Claim 11 (depends on 9)

The method of claim 9, further comprising:
transmitting, to the second memory device, a third set of signals comprising the data after transmitting the second set of signals.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
transferring the data from the set of buffers to an array of memory cells of the first memory device.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
receiving, at the first memory device via the first interface, a fourth set of signals comprising second data from a third memory device, the fourth set of signals modulated according to the first modulation scheme using the first quantity of voltage levels, wherein the third memory device is configured for access operations.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
transmitting the second set of signals using a burst length based at least in part on the second modulation scheme.

### Claim 15

An apparatus, comprising:
a first memory device comprising a first plurality of memory cells;
a second memory device comprising a second plurality of memory cells; and
a controller coupled with the first memory device and the second memory device, the controller operable to cause the apparatus to:
receive, from a host device, command and address information associated with a set of data, the command and address information being received using a first channel and a buffer included in the first memory device, wherein the first channel is configured to support a first modulation scheme using a first Quantity of voltage levels;
determine that the set of data is stored in the first plurality of memory cells; and
transmit, to the first memory device and based at least in part on determining that the set of data is stored in the first plurality of memory cells, a command to cause the first memory device to transmit the set of data to the second memory device using a second channel, wherein the second channel is configured to support a second modulation scheme using a second Quantity of voltage levels that is different than the first quantity of voltage levels.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein:
the first channel is configured to support a binary symbol modulation scheme selected from NRZ encoding, unipolar encoding, bipolar encoding, Manchester encoding, and PAM2 encoding; and
the second channel is configured to support a multi-symbol modulation scheme selected from PAM3, PAM4, PAM5, PAM6, PAM7, PAM8, PAM2y (y>3), quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK).

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the controller is further operable to cause the apparatus to:
transmit, to the second memory device and based at least in part on the set of data being transmitted to the second memory device, a second command to cause the second memory device to transmit the set of data to the host device.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the controller is further operable to cause the apparatus to:
update a logical address associated with the set of data based at least in part on transmitting the command.

### Claim 19 (depends on 15)

The apparatus of claim 15, wherein the controller is further operable to cause the apparatus to:
receive, from the host device, second command and address information associated with a second set of data;
determine that the second set of data is stored in the second plurality of memory cells; and
transmit, to the second memory device and based at least in part on determining that the second set of data is stored in the second plurality of memory cells, a third command to cause the second memory device to transmit the set of data to the host device.