# US 11,907,545 B2 · On-the-fly multiplexing scheme for compressed soft bit data in non-volatile memories

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- Number: US 11,907,545 B2
- Document ID: US11907545B2
- Status: Granted
- Kind: B2
- Application number: 17/731,971
- Filed: 2022-04-28
- Published: 2023-03-30
- Granted: 2024-02-20
- Earliest claimed: 2021-09-16
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: YenLung Li; Siddarth Naga Murty Bassa; Chen Chen; Hua-Ling Cynthia Hsu
- Web page: https://patentgrep.com/patent/US11907545B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F 3/0617: {in relation to availability}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0658: {Controller construction arrangements}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 29/76: {using address translation or modifications}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2029/0411: {Online error correction}
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

## Claims

### Claim 1

A non-volatile memory device, comprising:
a control circuit configured to connect to a plurality of columns, each column comprising one or more bit lines each connected to a corresponding plurality of memory cells, the plurality of columns including a plurality of regular columns and one or more spare columns, the control circuit comprising:
a plurality of sense amplifiers each configured to read data from the memory cells connected to a corresponding one or more bit lines of the plurality of columns;
a plurality of sets of internal data latches, each set of internal data latches configured to store data associated with a corresponding one of the sense amplifiers; and
an input-output interface, including a plurality of data buffers, configured to provide data to an external data bus,
the control circuit configured to:
perform a read operation by each of the sense amplifiers on a plurality of memory cells;
store results of the read operation by each of the sense amplifiers in the corresponding set of internal data latches;
compress the results of the read operation by each of the sense amplifiers within the corresponding set of internal data latches;
transfer the compressed results of the read operation to the input-output interface;
re-order bits of the compressed results of the read operation;
subsequent to re-ordering the compressed results of the read operation, replace the compressed results of the read operation from defective ones of the regular columns with corresponding compressed results of the read operation from spare columns within the input-output interface by multiplexing the re-ordered bits of the compressed results of the read operation;
store the re-ordered bits of the compressed results with the compressed results of the read operation from defective ones of the regular columns replaced with corresponding compressed results of the read operation from spare columns in the plurality of data buffers; and
transfer the compressed results of the read operation, including replaced compressed results of the read operation, from the plurality of data buffers to the external data bus.

### Claim 2 (depends on 1)

The non-volatile memory device of claim 1, wherein the control circuit is formed on a control die, the non-volatile memory device further comprising:
a memory die including the plurality of bit lines and corresponding pluralities of non-volatile memory cells, the memory die formed separately from and bonded to the control die.

### Claim 3 (depends on 1)

The non-volatile memory device of claim 1, wherein the results of the read operation are soft bit data values.

### Claim 4 (depends on 3)

The non-volatile memory device of claim 3, wherein the control circuit is further configured to:
perform a hard bit read operation by each of the sense amplifiers on the plurality of memory cells to determine a hard bit value for each of the plurality of memory cells indicating whether the memory cell is either reliably in a first data state or unreliability in a second data state, wherein each of the soft bit data values correspond to one of the hard bit values and indicate the reliability value of memory cells determined to be in the second data state, but not for memory cells determined to be in the first data state.

### Claim 5 (depends on 1)

The non-volatile memory of claim 1, the control circuit further comprising:
an internal data bus connecting the plurality of sets of internal data latches to the input-output interface,
wherein the plurality of data buffers are first in, first out data buffers (FIFOs) and the input-output interface further includes:
logic circuitry;
multiplexing circuitry,
wherein the control circuit is further configured to:
receive the compressed results of the read operation at the logic circuitry from the internal data bus;
perform the re-ordering of the bits of the compressed results in the logic circuitry; and
perform the replacement of the compressed results of the read operation from defective ones of the regular columns with the corresponding compressed results of the read operation from the spare columns by the multiplexing circuitry from the re-ordered bits of the compressed results of the read operation stored.

### Claim 6 (depends on 5)

The non-volatile memory of claim 5, wherein the control circuit is further configured to:
partially re-order bits of the compressed results of the read operation prior to transferring the compressed results of the read operation over the internal data bus to the input-output interface.

### Claim 7 (depends on 1)

The non-volatile memory device of claim 1, wherein the control circuit is further configured to:
receive the compressed results of the read operation at the input-output interface in a parallel format; and
convert the compressed results of the read operation to a serial format prior to transferring the compressed results of the read operation to the external data bus.

### Claim 8 (depends on 1)

The non-volatile memory device of claim 1, wherein, to compress the results of the read operation by each of the sense amplifiers within the corresponding set of internal data latches, the control circuit is further configured to:
perform logical combinations of multiple ones of the results of the read operation by each of the sense amplifiers.

### Claim 9 (depends on 1)

The non-volatile memory device of claim 1, further comprising:
an array of non-volatile memory cells, including the plurality bit lines each corresponding pluralities of memory cells, formed according to a three dimensional NAND architecture.

### Claim 10

A method, comprising:
performing a read operation by each of a plurality of sense amplifiers on a plurality of memory cells, each sense amplifiers configured to read data from the memory cells connected to a corresponding one or more bit lines, the bits forming of a plurality of columns including a plurality of regular columns and one or more spare columns;
storing results of the read operation by each of the sense amplifiers in a corresponding set of internal data latches;
performing, within the corresponding set of internal data latches, a data compression operation of the results of the read operations by each of the sense amplifiers;
re-ordering bits of the compressed results of the read operation;
subsequent to re-ordering bits of the compressed results of the read operation, replacing the compressed results of the read operation from defective ones of the regular columns with corresponding compressed results of the read operation from spare columns by multiplexing circuitry on the re-ordered bits of the compressed results of the read operation;
storing the re-ordered bits of the compressed results with the compressed results of the read operation from defective ones of the regular columns replaced with corresponding compressed results of the read operation from spare columns in a plurality of first in, first out data buffers (FIFOs); and
transferring the compressed results of the read operation, including replaced compressed results of the read operation, from the plurality of FIFOs to an external data bus.

### Claim 11 (depends on 10)

The method of claim 10, wherein the results of the read operation are soft bit data values.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
performing a hard bit read operation by each of the sense amplifiers on the plurality of memory cells to determine a hard bit value for each of the plurality of memory cells indicating whether the memory cell is either reliably in a first data state or unreliability in a second data state, wherein each of the soft bit data values correspond to one of the hard bit values and indicate a reliability value of memory cells determined to be in the second data state, but not for memory cells determined to be in the first data state.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
transferring the hard bit values and the corresponding soft bit data values to an error correction code engine.

### Claim 14

A non-volatile memory device, comprising:
a plurality of columns, each column comprising one or more bit lines each connected to a corresponding plurality of memory cells, the plurality of columns including a plurality of regular columns and one or more spare columns;
a plurality of sense amplifier circuits each configured to read data from memory connected to a corresponding one or more bit lines;
a plurality of sets of internal data latches, each set of internal data latches configured to store data associated with a corresponding one of the sense amplifiers;
an input-output interface, including a plurality of data buffers, configured to provide data to an external data bus; and
one or more control circuits connected to the sense amplifier circuits, the sets of internal data latches, and the input-output interface, the one or more control circuits configured to:
perform a read operation by each of the plurality of sense amplifiers on a plurality of the corresponding memory cells;
store results of the read operation by each of the sense amplifiers in the corresponding set of internal data latches;
compress, within the corresponding set of internal data latches, the results of the read operation by each of the sense amplifiers;
transfer the compressed results of the read operation to the input-output interface;
re-order bits of the compressed results of the read operation;
subsequent to re-ordering the compressed results of the read operation, replace the compressed results of the read operation from defective ones of the regular columns with corresponding compressed results of the read operation from spare columns within the input-output interface by multiplexing the re-ordered bits of the compressed results of the read operation;
store the re-ordered bits of the compressed results with the compressed results of the read operation from defective ones of the regular columns replaced with corresponding compressed results of the read operation from spare columns in the plurality of data buffers; and
transfer the compressed results of the read operation, including replaced compressed results of the read operation, from the plurality of data buffers to the external data bus.

### Claim 15 (depends on 14)

The non-volatile memory device of claim 14, further comprising:
an internal data bus connecting the plurality of sets of internal data latches to the input-output interface,
wherein the plurality of data buffers are first in, first out data buffers (FIFOs) and the input-output interface further includes:
logic circuitry;
and
multiplexing circuitry, and
wherein the one or more control circuits are further configured to:
receive the compressed results of the read operation at the logic circuitry from the internal data bus;
perform the re-ordering of the bits of the compressed results in the logic circuitry; and
perform the replacement of the compressed results of the read operation from defective ones of the regular columns with corresponding compressed results of the read operation from spare columns by the multiplexing circuitry on the re-ordered bits of the compressed results.

### Claim 16 (depends on 14)

The non-volatile memory device of claim 14, wherein the results of the read operation are soft bit data values.

### Claim 17 (depends on 14)

The non-volatile memory device of claim 14, wherein the non-volatile memory device includes:
a control die on which the one or more control circuits are formed; and
a memory die including the one or more bit lines and corresponding pluralities of non-volatile memory cells, the memory die formed separately from and bonded to the control die.

### Claim 18 (depends on 16)

The non-volatile memory device of claim 16, wherein the one or more control circuits are further configured to:
perform a hard bit read operation by each of the sense amplifiers on the plurality of memory cells to determine a hard bit value for each of the plurality of memory cells indicating whether the memory cell is either reliably in a first data state or unreliability in a second data state, wherein each of the soft bit data values correspond to one of the hard bit values and indicate the reliability value of memory cells determined to be in the second data state, but not for memory cells determined to be in the first data state.

### Claim 19 (depends on 18)

The non-volatile memory device of claim 18, wherein the one or more control circuits are further configured to:
transfer the hard bit values and the corresponding soft bit data values to an error correction code engine.

### Claim 20 (depends on 14)

The non-volatile memory device of claim 14, wherein the one or more control circuits are further configured to:
receive the compressed results of the read operation at the input-output interface in a parallel format; and
convert the compressed results of the read operation to a serial format prior to transferring the compressed results of the read operation to the external data bus.