# US 11,907,544 B2 · Automated error correction with memory refresh

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- Number: US 11,907,544 B2
- Document ID: US11907544B2
- Status: Granted
- Kind: B2
- Application number: 17/460,013
- Filed: 2021-08-27
- Published: 2022-03-03
- Granted: 2024-02-20
- Earliest claimed: 2020-08-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hyun Yoo Lee; Kang-Yong Kim
- Web page: https://patentgrep.com/patent/US11907544B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/0411: {Online error correction}
- G11C 2211/4062: Parity or ECC in refresh operations
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

## Claims

### Claim 1

A memory device comprising:
at least one memory array comprising multiple memory cells;
at least one buffer memory;
error logic coupled to the at least one memory array and the at least one buffer memory, the error logic configured to:
determine that data for a read operation includes at least one error, the data corresponding to an address that is associated with the at least one memory array; and
store at least part of the address in the at least one buffer memory based on the at least one error; and
refresh control circuitry coupled to the at least one memory array and configured to:
determine a refresh address for a refresh operation on the at least one memory array; and
write corrected data at the address of the at least one memory array based on the refresh address at least partially matching the address stored in the at least one buffer memory.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the at least one buffer memory comprises at least one latch.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the at least one buffer memory comprises an array of memory storage locations.

### Claim 4 (depends on 1)

The memory device of claim 1, further comprising:
control circuitry configured to read the data from the at least one memory array responsive to a read command that indicates the address.

### Claim 5 (depends on 4)

The memory device of claim 4, further comprising:
an interface configured to couple to an interconnect that is coupled to a host device, wherein:
the error logic is coupled to the interface; and
the error logic is configured to:
forward the corrected data to the interface responsive to the read command.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein:
the error logic comprises error correction code (ECC) circuitry; and
the ECC circuitry is configured to determine that the data includes the at least one error using an ECC value corresponding to the data.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the at least one memory array is configured to store the data in association with the ECC value that corresponds to the data.

### Claim 8 (depends on 6)

The memory device of claim 6, wherein:
the at least one memory array comprises multiple memory banks;
the ECC circuitry comprises an ECC engine; and
the ECC engine is configured to determine ECC values for different memory banks of the multiple memory banks to share the ECC circuitry between two or more memory banks.

### Claim 9 (depends on 6)

The memory device of claim 6, wherein:
the at least one memory array comprises multiple memory banks;
the ECC circuitry comprises multiple ECC engines;
respective ECC engines of the multiple ECC engines are coupled to respective memory banks of the multiple memory banks; and
a respective ECC engine is configured to determine ECC values for a respective memory bank of the multiple memory banks.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the error logic, in conjunction with the refresh control circuitry, is configured to:
write the corrected data at the address of the at least one memory array as part of a read-modify-write operation.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the error logic, in conjunction with the refresh control circuitry, is configured to:
store the corrected data in the at least one buffer memory in association with at least part of the address; and
write the corrected data at the address of the at least one memory array using the corrected data that is stored in the at least one buffer memory.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein:
the refresh control circuitry is configured to perform one or more refresh operations on the at least one memory array.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the one or more refresh operations comprise one or more self-refresh operations.

### Claim 14 (depends on 12)

The memory device of claim 12, wherein the refresh control circuitry and the error logic are jointly configured to:
write the corrected data at the address of the at least one memory array based on the refresh address.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the refresh control circuitry and the error logic are jointly configured to:
compare at least a portion of the refresh address to at least a portion of the address stored in the at least one buffer memory; and
write the corrected data at the address of the at least one memory array based on the comparison.

### Claim 16 (depends on 1)

The memory device of claim 1, further comprising:
control circuitry configured to enable or disable at least one of the error logic or the refresh control circuitry to write the corrected data at the address of the at least one memory array based on at least one command received from a host device.

### Claim 17 (depends on 1)

The memory device of claim 1, wherein the memory device comprises low-power double data rate (LPDDR) synchronous dynamic random-access memory (SDRAM).

### Claim 18 (depends on 1)

The memory device of claim 1, wherein the memory device comprises at least one die.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein the memory device comprises a memory module with multiple memory dies that include the at least one die.

### Claim 20

A method comprising:
determining that data for a read operation includes at least one error, the data corresponding to an address associated with at least one memory array;
storing at least part of the address in at least one buffer memory based on the determining of the at least one error;
after the storing, determining a refresh address for a refresh operation on the at least one memory array; and
writing corrected data at the address of the at least one memory array based on the refresh address at least partially matching the address stored in the at least one buffer memory.

### Claim 21 (depends on 20)

The method of claim 20, further comprising:
reading the data responsive to a read command; and
determining that the data includes the at least one error based on the reading.

### Claim 22 (depends on 21)

The method of claim 21, further comprising:
forwarding the corrected data to an interface coupled to an interconnect based on the determining that the data includes the at least one error and responsive to the read command.

### Claim 23 (depends on 20)

The method of claim 20, further comprising:
comparing at least a portion of the refresh address to at least a portion of the address stored in the at least one buffer memory; and
writing the corrected data at the address of the at least one memory array based on the comparing.

### Claim 24 (depends on 20)

The method of claim 20, further comprising:
latching the at least part of the address to retain the address.

### Claim 25 (depends on 20)

The method of claim 20, further comprising:
determining the corrected data using at least one error correction code (ECC) process.

### Claim 26 (depends on 20)

The method of claim 20, further comprising:
sensing other data as part of at least one refresh operation for another address of the at least one memory array; and
determining that the other data includes at least one other error based on the sensing.

### Claim 27 (depends on 26)

The method of claim 26, further comprising:
writing other corrected data at the other address of the at least one memory array as part of another refresh operation,
wherein the other refresh operation and the at least one refresh operation are a same refresh operation.

### Claim 28 (depends on 26)

The method of claim 26, further comprising:
writing other corrected data at the other address of the at least one memory array as part of another refresh operation,
wherein the at least one refresh operation precedes the other refresh operation.

### Claim 29 (depends on 26)

The method of claim 26, further comprising:
checking data integrity at consecutive refresh addresses as part of the at least one refresh operation.

### Claim 30 (depends on 26)

The method of claim 26, further comprising:
checking data integrity at nonconsecutive refresh addresses as part of the at least one refresh operation.

### Claim 31

A method comprising:
receiving a read command from an interconnect via an interface, the read command including an address;
reading data from at least one memory array based on the address included in the read command;
checking integrity of the data based on at least one error correction code (ECC) value;
determining that the data includes at least one error based on the checking;
storing at least part of the address based on the determining; and
writing corrected data at the address of the at least one memory array in conjunction with a refresh operation and based on the storing.

### Claim 32 (depends on 31)

The method of claim 31, further comprising:
determining a refresh address for the refresh operation on the at least one memory array;
comparing at least a portion of the refresh address to at least a portion of the address that is stored; and
determining the corrected data using the data and the ECC value based on the comparing.

### Claim 33 (depends on 31)

The method of claim 31, further comprising:
determining the corrected data using the data and the ECC value based on the determining that the data includes the at least one error and responsive to the read command; and
providing the corrected data to the interconnect via the interface.

### Claim 34

An apparatus comprising:
at least one memory array;
error correction code (ECC) logic configured to perform an ECC process for data stored in the at least one memory array;
a buffer memory; and
control circuitry that is configured to perform an automated error correction process with memory refresh, the automated error correction process comprising:
determining that a memory address of the at least one memory array is associated with at least one bit-error during a read operation using the ECC logic, the read operation corresponding to an external data access request;
writing the memory address to the buffer memory;
entering a self-refresh mode for the at least one memory array;
determining that a refresh address matches the memory address; and
correcting the at least one bit-error in conjunction with refreshing one or more memory cells that are represented by the refresh address.

### Claim 35 (depends on 34)

The apparatus of claim 34, wherein the apparatus includes a memory device comprising low-power double data rate synchronous dynamic random-access memory (LPDDR SDRAM).

### Claim 36 (depends on 34)

The apparatus of claim 34, wherein the buffer memory comprises a latch circuit.

### Claim 37

A method comprising:
operating a package comprising one or more memory dies in an architecture in which an error correction code (ECC) process is automated in response to-a self-refresh commands;
determining that a memory address has at least one bit-error during a read operation based on at least one ECC value, the read operation corresponding to an external data access request;
writing the memory address to a buffer memory;
entering a self-refresh mode in response to a self-refresh command;
determining that a self-refresh address matches the memory address; and
correcting the at least one bit-error responsive to refreshing one or more memory cells represented by the self-refresh address based on the determining that the self-refresh address matches the memory address.

### Claim 38 (depends on 37)

The method of claim 37, wherein the one or more memory dies comprise low-power dynamic random-access memory (DRAM).