# US 11,907,538 B2 · Extended utilization area for a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,538 B2 - Document ID: US11907538B2 - Status: Granted - Kind: B2 - Application number: 18/045,067 - Filed: 2022-10-07 - Published: 2023-03-02 - Granted: 2024-02-20 - Earliest claimed: 2008-02-28 - Assignees: Memory Technologies LLC - Applicants: Memory Technologies LLC - Inventors: Jani Hyvonen; Kimmo J. Mylly; Jussi Hakkinen; Yevgen Gyl - Web page: https://patentgrep.com/patent/US11907538B2 ## CPC - G06F 3/061: {Improving I/O performance} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F 12/0646: {Configuration or reconfiguration} - G06F 12/1458: {by checking the subject access rights} - G06F 13/1694: {Configuration of memory controller to different memory types} - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G06F 12/1433: {for a module or a part of a module} - G06F 12/1441: {for a range} - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G06F 2212/1052: Security improvement - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof. ## Claims ### Claim 1 A memory device comprising: a memory configured to be accessed according to a plurality of predefined access types, the plurality of predefined access types including at least a sequential access type; and a controller configured to: receive, from a host device, at least one first command to configure access to the memory device in accordance with the at least one of the plurality of predefined access types such that at least a portion of the memory is configured according to the at least one of the plurality of predefined access types for at least one usage; receive, after the at least one first command, at least one second command to activate the at least one of the plurality of predefined access types associated with the memory device; and receive, after the at least one second command, at least one third command to write data to the portion of the memory according to the activated at least one of the plurality of predefined access types. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the controller is further configured to: receive at least one fourth command to read from the memory according to the activated at least one of the plurality of predefined access types. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the at least one second command is used to access the memory. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the at least one second command activates two or more of the plurality of predefined access types in parallel. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the plurality of predefined access types comprises a default access type. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the default access type is preselected. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the memory comprises NAND memory and the at least the portion of the memory comprises a block of the NAND memory. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the controller is further configured to: conduct two or more simultaneous memory access operations. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the controller is further configured to: receive at least one fourth command to designate the at least one of the plurality of predefined access types associated with the memory device. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the at least the portion of the memory comprises a partition of the memory. ### Claim 11 (depends on 1) The memory device of claim 1, wherein the controller is further configured to: receive at least one fourth command to configure access to the memory device in accordance with a second one of the plurality of predefined access types such that at least a second portion of the memory is configured according to the second one of the plurality of predefined access types for at least one usage; and receive at least one fifth command to activate the second one of the plurality of predefined access types associated with the memory device. ### Claim 12 (depends on 1) The memory device of claim 1, further comprising one or more registers storing at least one of: (i) an indication of the plurality of predefined access types, (ii) the at least one of the plurality of predefined access types, or (iii) an at least one currently active predefined access type. ### Claim 13 A method comprising: receiving, by a controller of a memory device and from a host device at a first time, at least one first command to configure access to the memory device in accordance with at least one of a plurality of predefined access types; configuring, based at least in part on the at least one first command, at least a portion of a memory of the memory device according to the at least one of the plurality of predefined access types for at least one usage; receiving, at a second time after the first time, at least one second command to activate the at least one of the plurality of predefined access types associated with the memory device; activating, based at least in part on the at least one second command, the at least one of the plurality of predefined access types associated with the memory device; receiving, after the at least one second command, at least one third command to write data to the portion of the memory device according to the activated at least one of the plurality of predefined access types; and writing, based at least in part on the at least one third command, data to the portion of the memory according to the activated at least one of the plurality of predefined access types. ### Claim 14 (depends on 13) The method of claim 13, wherein the memory comprises NAND memory and the at least the portion of the memory comprises a block of the NAND memory. ### Claim 15 (depends on 13) The method of claim 13, wherein the at least one first command instructs configuring two or more of the plurality of predefined access types in parallel. ### Claim 16 (depends on 13) The method of claim 13, further comprising: receiving at least one fourth command to configure access to the memory device in accordance with a second one of the plurality of predefined access types such that at least a second portion of the memory is configured according to the second one of the plurality of predefined access types for at least one usage; and receive at least one fifth command to activate the second one of the plurality of predefined access types associated with the memory device. ### Claim 17 (depends on 13) The method of claim 13, wherein at least the portion of the memory comprises a partition of the memory. ### Claim 18 A host device, comprising: an interface to couple the host device to a memory device having a memory configured to be accessed according to a plurality of predefined access types; and a controller configured with logic instructions to: send at least one first command to configure access to the memory device in accordance with the at least one of the plurality of predefined access types such that at least a portion of the memory is configured according to the at least one of the plurality of predefined access types for at least one usage; send, after the at least one first command, at least one second command to activate the at least one of the plurality of predefined access types associated with the memory device; and send, after the at least one second command, at least one third command to write data to the portion of the memory according to the at least one of the plurality of predefined access types. ### Claim 19 (depends on 18) The host device of claim 18, wherein the at least one second command activates two or more of the plurality of predefined access types in parallel. ### Claim 20 (depends on 18) The host device of claim 18, wherein the controller is further configured with the logic instructions to: read one or more registers of the memory device to determine an indication of the plurality of predefined access types.