# US 11,907,528 B2 · Multi-processor bridge with cache allocate awareness

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,907,528 B2
- Document ID: US11907528B2
- Status: Granted
- Kind: B2
- Application number: 17/380,297
- Filed: 2021-07-20
- Published: 2021-11-11
- Granted: 2024-02-20
- Earliest claimed: 2018-10-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Kai Chirca; Daniel Wu; Matthew David Pierson
- Web page: https://patentgrep.com/patent/US11907528B2

## CPC

- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}
- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/064: {Management of blocks}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30123: {according to context, e.g. thread buffers}
- G06F 9/3897: {with adaptable data path}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5016: {the resource being the memory}
- G06F 12/0607: {Interleaved addressing}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0857: {by multiple requestors}
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/10: Address translation
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 13/124: {where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine}
- G06F 13/1642: {with request queuing}
- G06F 13/1663: {Access to shared memory}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)}
- H03M 13/015: {Simulation or testing of codes, e.g. bit error rate [BER] measurements}
- H03M 13/098: {using single parity bit}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/276: {Interleaving address generation}
- H03M 13/2785: {Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F 12/0851: {Cache with interleaved addressing}
- G06F 12/0862: with prefetch
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1048: Scalability
- G06F 2212/304: In main memory subsystem
- G06F 2212/452: Instruction code
- G06F 2212/6024: History based prefetching
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

## Claims

### Claim 1

A processing system comprising:
a plurality of processors including a first processor;
a cache memory coupled to the plurality of processors; and
a shared memory controller comprising:
circuitry configured to receive a memory management command having a specification to perform a memory management operation to load data into a memory location of the cache memory before the first processor executes an input/output instruction that requests the data from the memory location;
formatting circuitry configured to format the memory management command into a formatted command; and
routing circuitry configured to route the formatted command based on the specification; and
response circuitry configured to receive a response indicating the data was loaded into the memory location.

### Claim 2 (depends on 1)

The processing system of claim 1, wherein:
each of the plurality of processors shares the cache memory; and
the first processor and a second processor share the memory location of the cache memory.

### Claim 3 (depends on 1)

The processing system of claim 1, wherein:
the memory management command is a cache request.

### Claim 4 (depends on 1)

The processing system of claim 1, wherein:
the cache memory comprises an internal cache memory of the shared memory controller.

### Claim 5 (depends on 1)

The processing system of claim 1, wherein:
the routing circuitry is configured to route the formatted command to memory controller associated with the cache memory; and
the response circuitry is configured to receive the response from the memory controller.

### Claim 6 (depends on 1)

The processing system of claim 1, further comprising a badge circuit,
wherein a third processor of the plurality of processors is coupled to the cache memory by the bridge circuit.

### Claim 7 (depends on 6)

The processing system of claim 6, wherein:
the formatting circuitry is configured to format a second memory management command into a second formatted command configured for the bridge circuit;
the routing circuitry is configured to route the second formatted command to the bridge circuit;
the bridge circuit is configured to translate the second formatted command into an op code; and
the bridge circuit is configured to transmit the op code to a memory interface of the third processor.

### Claim 8 (depends on 1)

The processing system of claim 1, wherein:
the cache memory is an L2 cache memory.

### Claim 9 (depends on 1)

The processing system of claim 1, wherein:
the cache memory is an L3 cache memory; and
the response circuitry is configured to receive the response from the L3 cache memory.

### Claim 10

A method comprising:
receiving, by a shared memory controller, a memory management command having a specification to perform a memory management operation to load data into a memory location of a cache memory before a first processor of a plurality of processors executes an input/output instruction that requests the data from the memory location;
formatting, by formatting circuitry, the memory management command into a formatted command;
routing, by routing circuitry, the formatted command based on the specification;
receiving, by response circuitry, a response indicating the data was loaded into the memory location.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
each of the plurality of processors shares the cache memory; and
the first processor and a second processor of the plurality of processors share the memory location of the cache memory.

### Claim 12 (depends on 10)

The method of claim 10, wherein:
the memory management command is a cache request.

### Claim 13 (depends on 10)

The method of claim 10, wherein:
the cache memory comprises an internal cache memory of the shared memory controller.

### Claim 14 (depends on 10)

The method of claim 10, wherein:
routing the formatted command comprises the formatted command to a memory controller associated with the cache memory; and
receiving the response comprises receiving the response from the memory controller.

### Claim 15 (depends on 10)

The method of claim 10, wherein:
a third processor of the plurality of processors is coupled to the cache memory by a bridge circuit.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
formatting a second memory management command into a second formatted command configured for the bridge circuit;
routing the second formatted command to the bridge circuit;
translating, by the bridge circuit the second formatted command into an op code; and
transmitting, by the bridge circuit, the op code to a memory interface of the third processor.

### Claim 17 (depends on 10)

The method of claim 10, wherein:
the cache memory is an L2 cache memory.

### Claim 18 (depends on 10)

The method of claim 10, wherein:
the cache memory is an L3 cache memory; and
receiving the response comprises receiving the response from the L3 cache memory.

### Claim 19

A processing system comprising:
a plurality of processors including a first processor and a second processor, wherein the second processor includes a memory interface;
a cache memory coupled to the plurality of processors;
a bridge circuit, wherein the second processor is coupled to the cache memory by the bridge circuit; and
a shared memory controller comprising:
circuitry configured to receive a memory management command having a specification to perform a memory management operation to load data into a memory location of the cache memory before the first processor executes an input/output instruction that requests the data from the memory location;
formatting circuitry configured to format the memory management command into a formatted command; and
routing circuitry configured to route the formatted command based on the specification to the bridge circuit; and
response circuitry configured to receive a first response from the bridge circuit,
wherein the bridge circuit is configured to:
translate the formatted command into an op code;
transmit the op code to the memory interface of the second processor;
receive a second response from the second processor indicating the data was loaded into the memory location; and
send the first response to the response circuitry indicating the data was loaded into the memory location.

### Claim 20 (depends on 19)

The processing system of claim 19,
wherein the second response includes the data loaded into the memory location,
wherein the bridge circuit is configured to discard the data included in the second response, and
wherein the bridge circuit is configured to send the first response after receiving the second response.