# US 11,907,369 B2 · Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,369 B2 - Document ID: US11907369B2 - Status: Granted - Kind: B2 - Application number: 17/004,581 - Filed: 2020-08-27 - Published: 2022-03-03 - Granted: 2024-02-20 - Earliest claimed: 2020-08-27 - Assignees: Ventana Micro Systems Inc. - Applicants: Ventana Micro Systems Inc. - Inventors: John G. Favor; Srivatsan Srinivasan - Web page: https://patentgrep.com/patent/US11907369B2 ## CPC - G06F 21/56: Computer malware detection or handling, e.g. anti-virus arrangements - G06F 21/75: by inhibiting the analysis of circuitry or operation - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 21/556: {involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755)} - G06F 2212/60: Details of cache memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An out-of-order and speculative execution microprocessor that mitigates side channel attacks includes a cache memory and fill request generation logic that generates a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory. At least one execution pipeline receives first and second load operations, detects a condition in which the first load generates a need for an architectural exception, the second load misses in the cache memory, and the second load is newer in program order than the first load, and prevents state of the cache memory from being affected by the miss of the second load by inhibiting the fill request generation logic from generating a fill request for the second load or by canceling the fill request for the second load if the fill request generation logic has already generated the fill request for the second load. ## Claims ### Claim 1 A microprocessor that mitigates side channel attacks, comprising: a cache memory; fill request generation logic configured to generate a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory; wherein the processor is configured to perform speculative execution of instructions; wherein the processor is configured to execute instructions out of program order; and at least one execution pipeline configured to: receive first and second load operations; detect a condition in which the first load operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the first load operation; and prevent state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation; wherein to prevent the state of the cache memory from being affected by the miss of the second load operation means there are no side effects on the cache memory as a result of the miss of the second load operation in the cache memory. ### Claim 2 (depends on 1) The microprocessor of claim 1, wherein the cache memory comprises a directory that holds hashed address tags and page attribute information of cache lines present in the cache memory; wherein the directory provides a hit/miss prediction and the page attribute information based on the hashed address tags for use in determining the condition; and wherein the page attribute information and the hit/miss prediction are provided earlier in the at least one execution pipeline than a correct hit/miss indication. ### Claim 3 (depends on 2) The microprocessor of claim 2, wherein the cache memory and directory are virtually indexed and virtually tagged. ### Claim 4 (depends on 1) The microprocessor of claim 1, further comprising: a program order identifier, maintained by the at least one execution pipeline, that identifies a program order of an oldest operation that has generated a need for an architectural exception; and wherein to detect that the second load operation is newer in program order than the first load operation, the at least one execution pipeline compares a program order identifier associated with each received load operation with the maintained program order identifier. ### Claim 5 (depends on 4) The microprocessor of claim 4, wherein the at least one execution pipeline comprises a plurality of pipelines for concurrently executing a corresponding plurality of load operations; and wherein pipelines of the plurality share the maintained program order identifier. ### Claim 6 (depends on 1) The microprocessor of claim 1, wherein the first load operation generates the need for the architectural exception because a memory address specified by the first load operation is inaccessible or the first load operation does not have permission to access the memory address specified by the first load operation. ### Claim 7 (depends on 1) The microprocessor of claim 1, wherein the at least one execution pipeline is further configured to: receive a store operation that is older than the first load operation; detect a second condition in which the store operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the store operation; and prevent state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation. ### Claim 8 A method for mitigating side channel attacks in a microprocessor having a cache memory, at least one execution pipeline, and fill request generation logic configured to generate a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory, comprising: wherein the processor is configured to perform speculative execution of instructions; wherein the processor is configured to execute instructions out of program order; and receiving, by the at least one execution pipeline, first and second load operations; detecting, by the at least one execution pipeline, a condition in which the first load operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the first load operation; and preventing, by the at least one execution pipeline, state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation; wherein to prevent the state of the cache memory from being affected by the miss of the second load operation means there are no side effects on the cache memory as a result of the miss of the second load operation in the cache memory. ### Claim 9 (depends on 8) The method of claim 8, further comprising: wherein the cache memory comprises a directory that holds hashed address tags and page attribute information of cache lines present in the cache memory; providing, by the directory, a hit/miss prediction and the page attribute information based on the hashed address tags; using, by the at least one execution pipeline, the hit/miss prediction and the page attribute information of a predicted present cache line to determine the condition; and wherein the page attribute information and the hit/miss prediction are provided earlier in the at least one execution pipeline than a correct hit/miss indication. ### Claim 10 (depends on 9) The method of claim 9, wherein the cache memory and directory are virtually indexed and virtually tagged. ### Claim 11 (depends on 8) The method of claim 8, further comprising: maintaining, by the at least one execution pipeline, a program order identifier that identifies a program order of an oldest operation that has generated a need for an architectural exception; and wherein said detecting that the second load operation is newer in program order than the first load operation comprises comparing a program order identifier associated with each received load operation with the maintained program order identifier. ### Claim 12 (depends on 11) The method of claim 11, further comprising: wherein the at least one execution pipeline comprises a plurality of pipelines for concurrently executing a corresponding plurality of load operations; and sharing, by the pipelines of the plurality, the maintained program order identifier. ### Claim 13 (depends on 8) The method of claim 8, wherein the first load operation generates the need for the architectural exception because a memory address specified by the first load operation is inaccessible or the first load operation does not have permission to access the memory address specified by the first load operation. ### Claim 14 (depends on 8) The method of claim 8, further comprising: receiving, by the at least one execution pipeline, a store operation that is older than the first load operation; detecting, by the at least one execution pipeline, a second condition in which the store operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the store operation; and preventing, by the at least one execution pipeline, state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation. ### Claim 15 A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor for mitigating side channel attacks, the microprocessor having a cache memory, at least one execution pipeline, and fill request generation logic configured to generate a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory, wherein the microprocessor is configured by the instructions to perform operations comprising: wherein the processor is configured to perform speculative execution of instructions; wherein the processor is configured to execute instructions out of program order; and receiving, by the at least one execution pipeline, first and second load operations; detecting, by the at least one execution pipeline, a condition in which the first load operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the first load operation; and preventing, by the at least one execution pipeline, state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation; wherein to prevent the state of the cache memory from being affected by the miss of the second load operation means there are no side effects on the cache memory as a result of the miss of the second load operation in the cache memory. ### Claim 16 (depends on 15) The non-transitory computer medium of claim 15, the operations further comprising: wherein the cache memory comprises a directory that holds hashed address tags and page attribute information of cache lines present in the cache memory; providing, by the directory, a hit/miss prediction and the page attribute information based on the hashed address tags; using, by the at least one execution pipeline, the hit/miss prediction and the page attribute information of a predicted present cache line to determine the condition; and wherein the page attribute information and the hit/miss prediction are provided earlier in the at least one execution pipeline than a correct hit/miss indication. ### Claim 17 (depends on 16) The non-transitory computer medium of claim 16, wherein the cache memory and directory are virtually indexed and virtually tagged. ### Claim 18 (depends on 15) The non-transitory computer medium of claim 15, the operations further comprising: maintaining, by the at least one execution pipeline, a program order identifier that identifies a program order of an oldest operation that has generated a need for an architectural exception; and wherein said detecting that the second load operation is newer in program order than the first load operation comprises comparing a program order identifier associated with each received load operation with the maintained program order identifier. ### Claim 19 (depends on 18) The non-transitory computer medium of claim 18, the operations further comprising: wherein the at least one execution pipeline comprises a plurality of pipelines for concurrently executing a corresponding plurality of load operations; and sharing, by the pipelines of the plurality, the maintained program order identifier. ### Claim 20 (depends on 15) The non-transitory computer medium of claim 15, wherein the first load operation generates the need for the architectural exception because a memory address specified by the first load operation is inaccessible or the first load operation does not have permission to access the memory address specified by the first load operation. ### Claim 21 (depends on 15) The non-transitory computer medium of claim 15, the operations further comprising: receiving, by the at least one execution pipeline, a store operation that is older than the first load operation; detecting, by the at least one execution pipeline, a second condition in which the store operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the store operation; and preventing, by the at least one execution pipeline, state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation. ### Claim 22 (depends on 1) The microprocessor of claim 1, wherein said canceling the fill request for the second load operation comprises invalidating an entry occupied by the fill request in a fill request buffer of the microprocessor. ### Claim 23 (depends on 8) The method of claim 8, wherein said canceling the fill request for the second load operation comprises invalidating an entry occupied by the fill request in a fill request buffer of the microprocessor. ### Claim 24 (depends on 15) The non-transitory computer medium of claim 15, wherein said canceling the fill request for the second load operation comprises invalidating an entry occupied by the fill request in a fill request buffer of the microprocessor.