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US 11,907,158 B2Granted
Vector processor with vector first and multiple lane configuration
AssigneeMicron Technology, Inc.
InventorSteven Jeffrey Wallach
Life of this patent
Estimating the term…
Abstract
A vector processor with a vector first and multi-lane configuration. A vector operation for a vector processor can include a single vector or multiple vectors as input. Multiple lanes for the input can be used to accelerate the operation in parallel. And, a vector first configuration can enhance the multiple lanes by reducing the number of elements accessed in the lanes to perform the operation in parallel.
Claims20
An apparatus, comprising:
- a first vector register configured to store a first vector having first data elements of a predetermined number, the first vector register having a first lane and a second lane;
- a second vector register configured to store a second vector having second data elements of the predetermined number, the second vector register having a third lane and a fourth lane;
- a third register configured to store an index;
- a plurality of arithmetic logic units;
- a first circuit coupled from the first vector register to a first arithmetic logic unit of the plurality of arithmetic logic units and a second arithmetic logic unit of the plurality of arithmetic logic units, the first circuit configured to provide a first lane input to the first arithmetic logic unit to generate a first output vector, the first circuit configured to provide a second lane input to the second arithmetic logic unit to generate a second output vector, the first lane input and the second lane input including data elements selected according to the index from the first vector, wherein the first circuit comprises:
- a first multiplexor configured to receive first vector elements from the first lane of the first vector and output the first lane input to the first arithmetic logic unit;
- and
- a second multiplexor configured to receive second vector elements from the second lane of the first vector and output the second lane input to the second arithmetic logic unit;
- and
- a second circuit coupled from the second vector register to a third arithmetic logic unit of the plurality of arithmetic logic units, the second circuit further configured to provide a third lane input to the first arithmetic logic unit and a fourth lane input to the second arithmetic logic unit, the third lane input and the fourth lane input including data elements selected according to the index from the second vector.
7 more elements
An apparatus, comprising:
- a plurality of vector registers configured to store a plurality of vectors of data elements respectively;
- a register configured to store an index;
- a plurality of processing units configured to operate in parallel;
- and
- a circuit controlled by the register and coupled between the plurality of vector registers and the plurality of processing units, the circuit configured to provide a plurality of input vectors to the plurality of processing units respectively, wherein the circuit is configured to generate each respective input vector in the plurality of input vectors using:
- a first portion selected according to the index from a first lane and a second lane of a first vector register in the plurality of vector registers;
- and
- a second portion selected according to the index from a third lane and a fourth lane of a second vector register in the plurality of vector registers,
- wherein the circuit comprises:
- a first multiplexor configured to receive first data from the first lane of the first vector register and second data from the second lane of the first vector register and output a first lane input to a first processing unit of the plurality of processing units;
- a second multiplexor configured to receive third data from the first lane of the first vector register and fourth data from the second lane of the first vector register and output a second lane input to a second processing unit of the plurality of processing units;
- a third lane input to the first processing unit from a third multiplexor associated with the third lane of the second vector register, wherein the third multiplexor further outputs the third lane input to a third processing unit of the plurality of processing units;
- and
- a fourth lane input to the second processing unit from a fourth multiplexor associated with the fourth lane of the second vector register.
11 more elements
A method, comprising:
- storing, into a plurality of vector registers, a plurality of vectors of data elements respectively;
- storing, into a register, an index;
- generating, using a circuit controlled by the register and coupled between the plurality of vector registers and a plurality of processing units, a plurality of input vectors to the plurality of processing units respectively, wherein each respective input vector in the plurality of input vectors includes:
- a first portion selected according to the index from a first lane and a second lane of a first vector register in the plurality of vector registers;
- and
- a second portion selected according to the index from a third lane and a fourth lane of a second vector register in the plurality of vector registers,
- wherein the circuit comprises:
- a first multiplexor configured to receive first data from the first lane of the first vector register and second data from the second lane of the first vector register and output a first lane input into a first processing unit of the plurality of processing units;
- a second multiplexor configured to receive third data from the first lane of the first vector register and fourth data from the second lane of the first vector register and output a second lane input to a second processing unit of the plurality of processing units;
- a third lane input to the first processing unit from a third multiplexor associated with the third lane of the second vector register, wherein the third multiplexor further outputs the third lane input to a third processing unit of the plurality of processing units;
- and
- a fourth lane input to the second processing unit from a fourth multiplexor associated with the fourth lane of the second vector register;
- and
- processing, by the plurality of processing units, the plurality of input vectors in parallel.
11 more elements
Dependencies are inferred from the claim text.