# US 11,907,157 B2 · Reconfigurable processor circuit architecture

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- Number: US 11,907,157 B2
- Document ID: US11907157B2
- Status: Granted
- Kind: B2
- Application number: 18/092,247
- Filed: 2022-12-31
- Published: 2023-05-18
- Granted: 2024-02-20
- Earliest claimed: 2019-09-10
- Assignees: Cornami, Inc.
- Applicants: Cornami, Inc.
- Inventors: Paul L. Master; Steven K. Knapp; Raymond J. Andraka; Alexei Beliaev; Martin A. Franz; Rene Meessen; Frederick Curtis Furtek
- Web page: https://patentgrep.com/patent/US11907157B2

## CPC

- G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15})
- G06F 5/01: for shifting, e.g. justifying, scaling, normalising {(digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00)}
- G06F 7/487: Multiplying; Dividing {(G06F7/4833, G06F7/4836 take precedence)}
- G06F 7/4876: {Multiplying}
- G06F 7/50: Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence)
- G06F 7/52: Multiplying; Dividing (G06F7/483 - G06F7/491, G06F7/544 take precedence)
- G06F 7/523: Multiplying only
- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06F 9/30098: {Register arrangements}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/54: Interprogram communication
- G06F 15/7867: {with reconfigurable architecture}
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- G06F 2207/382: Reconfigurable for different fixed word lengths
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

## Claims

### Claim 1

A reconfigurable processor circuit comprising:
a first interconnection network;
a second interconnection network;
a processor coupled to the first interconnection network; and
a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network coupling adjacent computational cores of the plurality of computational cores, each computational core comprising:
a memory circuit;
a reconfigurable arithmetic circuit comprising:
at least one input reordering queue;
a configurable multiplier coupled to the at least one input reordering queue;
a configurable shifter and combiner network coupled to configurable multiplier; and
an accumulator circuit coupled to the configurable shifter and combiner network;
and
a zeros compression circuit comprising:
a zeros counter configured to count one or more sequential data packets having a zero data payload to generate a zeros count; and
a first data packet generator configured, when a next data packet has a nonzero data payload, to encode the zeros count as a suffix in the next data packet.

### Claim 2 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the first data packet generator is further configured to transmit the next data packet having the nonzero data payload on the first interconnection network or the second interconnection network and not to transmit the one or more data packets having the zero data payload on the first interconnection network and the second interconnection network.

### Claim 3 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the first data packet generator is further configured, when the zeros count has reached a predetermined zeros count and the next data packet has either a zero or a nonzero data payload, to encode the predetermined zeros count as the suffix in the next data packet.

### Claim 4 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the zeros counter is further configured to generate the zeros count up to a maximum zeros count, and when the zeros count has reached the maximum zeros count, the first data packet generator is further configured to encode the maximum zeros count as the suffix in the next data packet, the next data packet having either a zero or a nonzero data payload.

### Claim 5 (depends on 4)

The reconfigurable processor circuit of claim 4, wherein the zeros counter is further configured, when the maximum zeros count has been reached, to reset the zeros count to zero.

### Claim 6 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the reconfigurable arithmetic circuit further comprises:
a zeros decompression circuit configured to receive the next data packet, the zeros decompression circuit comprising:
a suffix counter configured to determine the zeros count from the suffix of the next data packet; and
a second data packet generator configured to generate the one or more data packets having a zero data payload, corresponding to the zeros count, before providing the next data packet having the nonzero data payload.

### Claim 7 (depends on 6)

The reconfigurable processor circuit of claim 6, wherein each computational core of the plurality of computational cores further comprises:
at least one input multiplexer coupled to the reconfigurable arithmetic circuit, to the first interconnection network, to the second interconnection network, and to the zeros decompression circuit;
at least one input register coupled to the at least one input multiplexer;
at least one output multiplexer coupled to the reconfigurable arithmetic circuit, to the zeros compression circuit, and to the at least one input register; and
at least one output register coupled to the at least one output multiplexer, to the first interconnection network, and to the second interconnection network.

### Claim 8 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the reconfigurable arithmetic circuit further comprises:
a comparator circuit coupled to the at least one input reordering queue, the comparator circuit configured to perform data steering.

### Claim 9 (depends on 8)

The reconfigurable processor circuit of claim 8, wherein the comparator circuit comprises:
a single-instruction multiple-data (SIMD) magnitude comparator configured to generate a comparison result from one or more comparisons;
a plurality of registers;
a plurality of steering multiplexers;
an adder or counter configured to generate one or more index counts; and
a programmable decoder coupled to the plurality of steering multiplexers, the programmable decoder configured, in response to the comparison result, to generate one or more control signals, of a plurality of control signals, to one or more steering multiplexers of the plurality of steering multiplexers, to control one or more data or counter paths.

### Claim 10 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the configurable multiplier has a plurality of operating modes, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs.

### Claim 11 (depends on 10)

The reconfigurable processor circuit of claim 10, further comprising:
a third interconnection network configured to selectively couple the shifter and combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 and 54×54 multiplication, single precision 24×24 multiplication, and single-instruction multiple-data (SIMD) dot products.

### Claim 12 (depends on 10)

The reconfigurable arithmetic circuit of claim 10, wherein the configurable multiplier is further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier.

### Claim 13 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the shifter and combiner network comprises:
a shifter circuit; and
a plurality of series-coupled adder circuits coupled to the shifter circuit;
wherein the shifter and combiner network is configured to shift a multiplier product to convert a floating point product to a product having a radix-32 exponent, and to sum a plurality of single-instruction multiple-data (SIMD) products to form a SIMD dot product.

### Claim 14 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the at least one input reordering queue is configured to store a plurality of inputs, and the at least one input reordering queue further comprise:
input reordering logic circuitry configured to reorder a sequence of the plurality of inputs, to adjust a sign bit for negate and absolute value functions, and to de-interleave in phase (I) and quadrature (Q) data inputs and odd and even data inputs.

### Claim 15 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the reconfigurable arithmetic circuit further comprises:
at least one output reorder queue coupled to receive and reorder outputs from a plurality of reconfigurable arithmetic circuits.

### Claim 16 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the reconfigurable arithmetic circuit has a plurality of inputs, the plurality of inputs comprising a first, X input; a second, Y input, and a third, Z input; and
wherein the reconfigurable arithmetic circuit further comprises:
at least one control logic circuit comprising one or more circuits selected from the group consisting of: a compare circuit; a Boolean logic circuit; a Z input shifter; an exponent logic circuit; an add, saturate and round circuit; and combinations thereof.

### Claim 17 (depends on 16)

The reconfigurable processor circuit of claim 16, wherein the Z input shifter is configured to shift a floating point Z-input value to a radix-32 exponent value, to shift by multiples of 32 bits to match a scaling of multiplier sum outputs, and wherein the Z input shifter is further configured for a plurality of integer modes including 64, 32, 2×16 and 4×8 bit shift or rotate modes.

### Claim 18 (depends on 16)

The reconfigurable processor circuit of claim 16, wherein the Boolean logic circuit comprises an AND-OR-INVERT logic unit configured to perform AND, NAND, OR, NOR, XOR, XNOR, and selector operations on 32 bit integer inputs.

### Claim 19 (depends on 16)

The reconfigurable processor circuit of claim 16, wherein the compare circuit is configured to extract a minimum or maximum data value from an input data stream, an index from the input data stream, to compare two input data streams, to swap two input data streams, to put the minimum of the two input data streams on a first output and to put the maximum of the two input data streams on a second output, to perform data steering, to generate address sequences, and to generate comparison flags for equality, greater than and less than.

### Claim 20 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein a single reconfigurable arithmetic circuit is configured to perform at least two mathematical computation or functions selected from the group consisting of: one IEEE single or integer 27×27 multiply per cycle; two parallel IEEE half precision, 16-bit brain floating point (“BFLOAT”) (BLOAT16), or 16-bit integer for signed and unsigned 16-bit integer values (INT16) multiplies per cycle; four parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; sum of two parallel IEEE half precision, BFLOAT16 or INT16 multiplies per cycle; sum of four parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; one quarter-precision or INT8 complex multiply per cycle; fused add; accumulation; 64, 32, 2×16 or 4×8 bit shifts by any number of bits; 64, 32, 2×16 or 4×8 bit rotate by any number of bits; 32-bit bitwise Boolean logic; compare, minimum or maximum of a data stream; two operand sort; and combinations thereof;
wherein two adjacent linked reconfigurable arithmetic circuits having a pair configuration are configured to perform at least two mathematical computation or functions selected from the group consisting of: one 32-bit integer for signed and unsigned 32-bit integer values (INT32) multiply per cycle; one 64-bit integer for signed and unsigned 64-bit integer values (INT64) multiply in a 4 cycle sequence using the accumulator circuit to add four 32×32 partial products; sum of two IEEE single precision or two 24-bit integer for signed and unsigned 24-bit integer values (INT24) multiplies per cycle; sum of four parallel IEEE half precision, 16-bit brain floating point (“BFLOAT”) (BLOAT16) or 16-bit integer for signed and unsigned 16-bit integer values (INT16) multiplies per cycle; sum of eight parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; one half-precision or INT16 complex multiply per cycle; four multiplies and two adds; fused add; accumulation; and combinations thereof; and
wherein four linked reconfigurable arithmetic circuits having a quad configuration are configured to perform at least two mathematical computation or functions selected from the group consisting of: two 64-bit integer for signed and unsigned 64-bit integer values (INT64) multiplies in four cycles; two 32-bit integer for signed and unsigned 32-bit integer values (INT32) multiplies per cycle; sum of two INT32 multiplies per cycle; sum of four IEEE single precision or 24-bit integer for signed and unsigned 24-bit integer values (INT24) per cycle; sum of eight parallel IEEE half precision, 16-bit brain floating point (“BFLOAT”) (BLOAT16) or 16-bit integer for signed and unsigned 16-bit integer values (INT16) multiplies per cycle; sum of sixteen parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; one single precision or 24-bit integer for signed and unsigned 24-bit integer values (INT24) complex multiply per cycle; fused add; accumulation; and combinations thereof.

### Claim 21

A reconfigurable processor circuit comprising:
a first interconnection network;
a second interconnection network;
a processor coupled to the first interconnection network; and
a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network coupling adjacent computational cores of the plurality of computational cores, each computational core comprising:
a memory circuit;
a reconfigurable arithmetic circuit comprising:
at least one input reordering queue;
a configurable multiplier coupled to the at least one input reordering queue;
a configurable shifter and combiner network coupled to configurable multiplier; and
an accumulator circuit coupled to the configurable shifter and combiner network;
a zeros compression circuit comprising:
a zeros counter configured to count one or more sequential data packets having a zero data payload to generate a zeros count; and
a first data packet generator configured, when a next data packet has a nonzero data payload, to encode the zeros count as a suffix in the next data packet, and further configured, when the zeros count has reached a predetermined zeros count and the next data packet has either a zero or a nonzero data payload, to encode the predetermined zeros count as the suffix in the next data packet;
and
a zeros decompression circuit configured to receive the next data packet from the first or second interconnection networks, the zeros decompression circuit comprising:
a suffix counter configured to determine the zeros count from the suffix of the next data packet; and
a second data packet generator configured to generate the one or more data packets having a zero data payload, corresponding to the zeros count, before providing the next data packet having the nonzero data payload.

### Claim 22 (depends on 21)

The reconfigurable processor circuit of claim 21, wherein the data packet generator is further configured to transmit the next data packet having the nonzero data payload on the first interconnection network or the second interconnection network and not to transmit the one or more data packets having the zero data payload on the first interconnection network and the second interconnection network.

### Claim 23 (depends on 21)

The reconfigurable processor circuit of claim 21, further comprising:
a third, configurable interconnection network coupled to the shifter and combiner network, the third, configurable interconnection network configured to merge a plurality of reconfigurable arithmetic circuits to perform double precision multiply-adds, single precision single cycle complex multiply, FFT butterfly, exponent resolution, multiply-accumulate, and logic operations.

### Claim 24 (depends on 21)

The reconfigurable processor circuit of claim 21, wherein the reconfigurable arithmetic circuit further comprises:
a comparator circuit coupled to the at least one input reordering queue, the comparator circuit configured to perform data steering, the comparator circuit comprising:
a single-instruction multiple-data (SIMD) magnitude comparator configured to generate a comparison result from one or more comparisons;
a plurality of registers;
a plurality of steering multiplexers;
an adder or counter configured to generate one or more index counts; and
a programmable decoder coupled to the plurality of steering multiplexers, the programmable decoder configured, in response to the comparison result, to generate one or more control signals, of a plurality of control signals, to one or more steering multiplexers of the plurality of steering multiplexers, to control one or more data or counter paths.

### Claim 25 (depends on 21)

The reconfigurable processor circuit of claim 21, wherein the configurable multiplier has a plurality of operating modes, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs.

### Claim 26 (depends on 21)

The reconfigurable processor circuit of claim 21, wherein the shifter and combiner network comprises:
a shifter circuit; and
a plurality of series-coupled adder circuits coupled to the shifter circuit;
wherein the shifter and combiner network is configured to shift a multiplier product to convert a floating point product to a product having a radix-32 exponent, and to sum a plurality of single-instruction multiple-data (SIMD) products to form a SIMD dot product.

### Claim 27 (depends on 21)

The reconfigurable processor circuit of claim 21, wherein the at least one input reordering queue is configured to store a plurality of inputs, and the at least one input reordering queue further comprise:
input reordering logic circuitry configured to reorder a sequence of the plurality of inputs, to adjust a sign bit for negate and absolute value functions, and to de-interleave in phase (I) and quadrature (Q) data inputs and odd and even data inputs;
and wherein the reconfigurable arithmetic circuit further comprises:
at least one output reorder queue coupled to receive and reorder outputs from a plurality of reconfigurable arithmetic circuits.

### Claim 28 (depends on 1)

The reconfigurable processor circuit of claim 1, wherein the reconfigurable arithmetic circuit has a plurality of inputs, the plurality of inputs comprising a first, X input; a second, Y input, and a third, Z input; and
wherein the reconfigurable arithmetic circuit further comprises:
at least one control logic circuit comprising one or more circuits selected from the group consisting of: a compare circuit; a Boolean logic circuit; a Z input shifter; an exponent logic circuit; an add, saturate and round circuit; and combinations thereof.

### Claim 29 (depends on 28)

The reconfigurable processor circuit of claim 28, wherein the Z input shifter is configured to shift a floating point Z-input value to a radix-32 exponent value, to shift by multiples of 32 bits to match a scaling of multiplier sum outputs, and wherein the Z input shifter is further configured for a plurality of integer modes including 64, 32, 2×16 and 4×8 bit shift or rotate modes.

### Claim 30 (depends on 28)

The reconfigurable processor circuit of claim 28, wherein the Boolean logic circuit comprises an AND-OR-INVERT logic unit configured to perform AND, NAND, OR, NOR, XOR, XNOR, and selector operations on 32 bit integer inputs.

### Claim 31 (depends on 28)

The reconfigurable processor circuit of claim 28, wherein the compare circuit is configured to extract a minimum or maximum data value from an input data stream, an index from the input data stream, to compare two input data streams, to swap two input data streams, to put the minimum of the two input data streams on a first output and to put the maximum of the two input data streams on a second output, to perform data steering, to generate address sequences, and to generate comparison flags for equality, greater than and less than.

### Claim 32

A reconfigurable processor circuit comprising:
a first interconnection network;
a second interconnection network;
a processor coupled to the first interconnection network; and
a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network configured to couple adjacent computational cores of the plurality of computational cores, each computational core comprising:
a memory circuit;
a zeros compression circuit comprising:
a zeros counter configured to count one or more sequential data packets having a zero data payload to generate a zeros count; and
a first data packet generator configured, when a next data packet has a nonzero data payload, to encode the zeros count as a suffix in the next data packet;
a zeros decompression circuit configured to receive the next data packet from the first or second interconnection networks, the zeros decompression circuit comprising:
a suffix counter configured to determine the zeros count from the suffix of the next data packet; and
a second data packet generator configured to generate the one or more data packets having a zero data payload, corresponding to the zeros count, before providing the next data packet having the nonzero data payload;
and
a reconfigurable arithmetic circuit comprising:
at least one input reordering queue configured to store a plurality of inputs, the at least one input reordering queue further comprising input reordering logic circuitry configured to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuit and an adjacent reconfigurable arithmetic circuit of an adjacent computational core of the plurality of computational cores;
a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the at least one input reordering queue, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, and wherein the configurable multiplier is further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier;
a shifter and combiner network coupled to the configurable multiplier, the shifter and combiner network comprising:
a shifter circuit; and
a plurality of series-coupled adder circuits coupled to the shifter circuit;
an accumulator circuit coupled to the shifter and combiner network;
at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit; and
at least one output reorder queue coupled to receive and reorder a plurality of outputs from the reconfigurable arithmetic circuit and the adjacent reconfigurable arithmetic circuit of the adjacent computational core of the plurality of computational cores.