# US 11,907,154 B2 · Latency and power efficient clock and data recovery in a high-speed one-wire bidirectional bus

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- Number: US 11,907,154 B2
- Document ID: US11907154B2
- Status: Granted
- Kind: B2
- Application number: 17/861,886
- Filed: 2022-07-11
- Published: 2024-01-11
- Granted: 2024-02-20
- Earliest claimed: 2022-07-11
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Lalan Jee Mishra; Umesh Srikantiah; Francesco Gatta; Muhlis Kenan Ozel; Richard Dominic Wietfeldt
- Web page: https://patentgrep.com/patent/US11907154B2

## CPC

- G06F 13/4068: {Electrical coupling}
- G06F 13/4295: {using an embedded synchronisation}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- H04L 7/0066: {detection of error based on transmission code rule}
- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 7/042: {Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15)}
- G06F 2213/40: Bus coupling
- H03M 5/12: Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
- H04L 7/041: {using special codes as synchronising signal}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

## Claims

### Claim 1

A clock and data recovery apparatus, comprising:
an oscillator configured to generate a base clock signal with a base frequency;
a clock gating circuit responsive to one or more control inputs and configured to output a gated base clock signal while the clock gating circuit is enabled;
a first counter clocked by the gated base clock signal and configured to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal;
control logic coupled to a first control input of the clock gating circuit and configured to disable the clock gating circuit when the counter output corresponds to a maximum count value; and
an edge synchronization circuit coupled to a one-wire bus and configured to:
ignore edges in a signal received from the one-wire bus while the counter output has a value that is less than the maximum count value; and
reset the first counter in response to an edge detected in the signal received from the one-wire bus.

### Claim 2 (depends on 1)

The clock and data recovery apparatus of claim 1, wherein the signal received from the one-wire bus is Manchester-encoded based on an encoding clock having a frequency that is four times greater than the base frequency of the base clock signal.

### Claim 3 (depends on 2)

The clock and data recovery apparatus of claim 2, wherein the encoding clock has a frequency of at least 52 MHz.

### Claim 4 (depends on 1)

The clock and data recovery apparatus of claim 1, further comprising:
a flipflop configured to capture a data bit from the one-wire bus in response to an edge detected in the signal received from the one-wire bus.

### Claim 5 (depends on 4)

The clock and data recovery apparatus of claim 4, wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flipflop.

### Claim 6 (depends on 1)

The clock and data recovery apparatus of claim 1, wherein a signal output by the control logic that disables the clock gating circuit is used to generate a write clock signal that is output by the clock and data recovery apparatus.

### Claim 7 (depends on 1)

The clock and data recovery apparatus of claim 1, further comprising:
a second counter clocked by the signal received from the one-wire bus and configured to drive a second control input of the clock gating circuit,
wherein the second counter is held in a reset state when the one-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the one-wire bus,
wherein the second counter is configured to halt counting when an expected number of synchronization pulses have been counted in the signal received from the one-wire bus, and
wherein the clock gating circuit is disabled until the second counter halts counting.

### Claim 8 (depends on 7)

The clock and data recovery apparatus of claim 7, wherein the second counter is reset when an output by the control logic that disables the clock gating circuit is used to generate a write clock signal that is output by the clock and data recovery apparatus.

### Claim 9 (depends on 1)

The clock and data recovery apparatus of claim 1, wherein the signal received from the one-wire bus carries a datagram configured in accordance with a Radio Frequency Front-End (RFFE) protocol and encoded using Manchester encoding.

### Claim 10

A method of data communication, comprising:
configuring an oscillator to generate a base clock signal with a base frequency;
configuring a clock gating circuit to output a gated base clock signal while the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs;
configuring a first counter to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal that clocks the first counter;
configuring control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and
configuring an edge synchronization circuit to:
ignore edges in a signal received by the edge synchronization circuit from a one-wire bus while the counter output has a value that is less than the maximum count value; and
reset the first counter in response to an edge detected in the signal received from the one-wire bus.

### Claim 11 (depends on 10)

The method of claim 10, wherein the signal received from the one-wire bus is Manchester-encoded based on an encoding clock having a frequency that is four times greater than the base frequency of the base clock signal.

### Claim 12 (depends on 11)

The method of claim 11, wherein the encoding clock has a frequency of at least 52 MHz.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
configuring a flipflop to capture a data bit from the one-wire bus in response to an edge detected in the signal received from the one-wire bus.

### Claim 14 (depends on 13)

The method of claim 13, wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flipflop.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
generating an output signal using a signal output by the control logic that disables the clock gating circuit, the output signal being configured to provide timing for writing data captured from the one-wire bus.

### Claim 16 (depends on 10)

The method of claim 10, further comprising:
configuring a second counter to drive a control input of the clock gating circuit, the second counter being clocked by the signal received from the one-wire bus,
wherein the second counter is held in a reset state when the one-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the one-wire bus,
wherein the second counter is configured to halt counting when an expected number of synchronization pulses have been counted in the signal received from the one-wire bus, and
wherein the clock gating circuit is disabled until the second counter halts counting.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second counter is reset when an output by the control logic that disables the clock gating circuit is used to generate an output signal configured to provide timing for writing data captured from the one-wire bus.

### Claim 18 (depends on 10)

The method of claim 10, wherein the signal received from the one-wire bus carries a datagram configured in accordance with a Radio Frequency Front-End (RFFE) protocol and encoded using Manchester encoding.

### Claim 19

A data communication apparatus, comprising:
means for generating a base clock signal with a base frequency;
means for gating the base clock signal, including a clock gating circuit responsive to one or more control inputs, the means for gating the base clock signal being configured to output a gated base clock signal while the clock gating circuit is enabled;
means for counting positive and negative edges in the gated base clock signal, including a first counter clocked by the gated base clock signal;
means for disabling the clock gating circuit, including control logic coupled to a first control input of the clock gating circuit, the means for disabling the clock gating circuit being configured to disable the clock gating circuit when an output of the first counter corresponds to a maximum count value; and
means for synchronizing the means for counting positive and negative edges in the signal received from a one-wire bus, configured to:
ignore edges in the signal received from the one-wire bus while the output of the first counter represents a value that is less than the maximum count value; and
reset the first counter in response to an edge detected in the signal received from the one-wire bus.

### Claim 20 (depends on 19)

The data communication apparatus of claim 19, wherein the signal received from the one-wire bus is Manchester-encoded based on an encoding clock having a frequency that is four times greater than the base frequency of the base clock signal.

### Claim 21 (depends on 20)

The data communication apparatus of claim 20, wherein the encoding clock has a frequency of at least 52 MHz.

### Claim 22 (depends on 19)

The data communication apparatus of claim 19, further comprising:
means for capturing data bits from the one-wire bus responsive to edges detected in the signal received from the one-wire bus.

### Claim 23 (depends on 22)

The data communication apparatus of claim 22, wherein the means for capturing data bits from the one-wire bus comprises a flipflop and wherein a signal output by the control logic that disables the clock gating circuit is used to clock the flipflop.

### Claim 24 (depends on 19)

The data communication apparatus of claim 19, wherein a signal output by the control logic that disables the clock gating circuit is used to generate a write clock signal that is output by the data communication apparatus.

### Claim 25 (depends on 19)

The data communication apparatus of claim 19, further comprising:
means for counting synchronization pulses, including a second counter clocked by the signal received from the one-wire bus, the means for counting synchronization pulses being configured to drive a second control input of the clock gating circuit,
wherein the second counter is held in a reset state when the one-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the one-wire bus,
wherein the means for counting synchronization pulses is configured to halt the second counter when an expected number of synchronization pulses have been counted in the signal received from the one-wire bus, and
wherein the clock gating circuit is disabled until the second counter halts counting.

### Claim 26 (depends on 25)

The data communication apparatus of claim 25, wherein the second counter is reset when an output by the control logic that disables the clock gating circuit is used to generate a write clock signal that is output by the data communication apparatus.

### Claim 27 (depends on 19)

The data communication apparatus of claim 19, wherein the signal received from the one-wire bus carries a datagram configured in accordance with a Radio Frequency Front-End (RFFE) protocol and encoded using Manchester encoding.

### Claim 28

A non-transitory processor-readable storage medium storing code thereon, the code when executed by a processor in a processing circuit causes the processing circuit to:
configure an oscillator to generate a base clock signal with a base frequency;
configure a clock gating circuit to output a gated base clock signal while the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs;
configure a first counter to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal that clocks the first counter;
configure control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and
configure an edge synchronization circuit to:
ignore edges in a signal received by the edge synchronization circuit from a one-wire bus while the counter output has a value that is less than the maximum count value; and
reset the first counter in response to an edge detected in the signal received from the one-wire bus.

### Claim 29 (depends on 28)

The non-transitory processor-readable storage medium of claim 28, wherein the signal received from the one-wire bus carries a Manchester-encoded datagram configured in accordance with a Radio Frequency Front-End (RFFE) protocol and encoded using an encoding clock having a frequency that is four times greater than the base frequency of the base clock signal.

### Claim 30 (depends on 28)

The non-transitory processor-readable storage medium of claim 28, wherein the code further causes the processing circuit to:
configure a second counter to drive a control input of the clock gating circuit, the second counter being clocked by the signal received from the one-wire bus,
wherein the second counter is held in a reset state when the one-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the one-wire bus,
wherein the second counter is configured to halt counting when an expected number of synchronization pulses have been counted in the signal received from the one-wire bus, and
wherein the clock gating circuit is disabled until the second counter halts counting.