# US 11,907,152 B2 · Reconfigurable server and server rack with same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,152 B2 - Document ID: US11907152B2 - Status: Granted - Kind: B2 - Application number: 17/989,694 - Filed: 2022-11-18 - Published: 2023-03-16 - Granted: 2024-02-20 - Earliest claimed: 2017-05-15 - Assignees: Molex Incorporated - Applicants: Molex, LLC - Inventors: Augusto Panella; Allan Cantle; Ray Matyka; John W. Comish, Jr. - Web page: https://patentgrep.com/patent/US11907152B2 ## CPC - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 15/76: Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) - G06F 13/1668: {Details of memory controller} - G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices} - G06F 13/4068: {Electrical coupling} - G06F 13/423: {with synchronous protocol} - G06F 13/4243: {with synchronous protocol} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 15/16: Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor G06F9/52; in regulating and control system G05B)} - H04Q 1/04: Frames or mounting racks for selector switches; Accessories therefor, e.g. frame cover - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W) ## Abstract A reconfigurable server includes improved bandwidth connection to adjacent servers and allows for improved access to near-memory storage and for an improved ability to provision resources for an adjacent server. The server includes processor array and a near-memory accelerator module that includes near-memory and the near-memory accelerator module helps provide sufficient bandwidth between the processor array and near-memory. A hardware plane module can be used to provide additional bandwidth and interconnectivity between adjacent servers and/or adjacent switches. ## Claims ### Claim 1 A reconfigurable server, comprising: main memory; a processor module with a processor array, the processor array connected to the main memory and having a plurality of peripheral interconnect channels supporting a first communication protocol that is serial and a plurality of high data rate capable channels supporting a second communication protocol different than the first communication protocol; a near-memory accelerator module connected to one of the high data rate capable channels, the near-memory accelerator module having a programmable logic device (PLD) that is a field programmable gate array (FPGA), wherein the PLD is connected to one of the high data rate capable channels and the PLD is connected to a peripheral interconnect switch with a predetermined number of interconnect lanes, the peripheral interconnect switch connected to a near-memory module with the predetermined number of interconnect lanes, wherein a bandwidth between the PLD and the near-memory module is only within ten percent of a bandwidth between the PLD and the processor array. ### Claim 2 (depends on 1) The reconfigurable server of claim 1, wherein a link between the processor array and the PLD supports a data rate of 25 Gigabytes per second (GB/s). ### Claim 3 (depends on 2) The reconfigurable server of claim 2, wherein the bandwidth between the PLD and the near-memory module is 32 GB/s. ### Claim 4 (depends on 1) The reconfigurable server of claim 1, wherein the near-memory accelerator module comprises a plurality of near-memory accelerator modules, each one of the plurality of near-memory accelerator modules connected to one of the high data rate capable channels. ### Claim 5 (depends on 4) The reconfigurable server of claim 4, wherein a connection between the processor array and the near-memory modules provides 100 GB/s of bandwidth. ### Claim 6 (depends on 4) The reconfigurable server of claim 4, wherein a connection between the processor array and the near-memory modules provides 200 GB/s of bandwidth. ### Claim 7 (depends on 4) The reconfigurable server of claim 4, further comprising a peripheral interconnect expander module connected to a portion of the plurality of peripheral interconnect channels extending from the processor array, the peripheral interconnect expander module comprising a second peripheral interconnect switch that connects the portion of the plurality of peripheral interconnect channels from the processor array to peripheral interconnect channels extending between the second peripheral interconnect switch and the PLDs in the plurality of near-memory accelerator modules. ### Claim 8 (depends on 1) The reconfigurable server of claim 1, wherein the near-memory accelerator module further comprises a connector connected to the PLD, the connector configured to be connected to another server and supporting 100 Gbps data rate. ### Claim 9 (depends on 8) The reconfigurable server of claim 8, wherein the connector is a quad small form factor pluggable (QSFP) style connector. ### Claim 10 A reconfigurable server, comprising: main memory; a processor module with a processor array, the processor array connected to the main memory and having a plurality of peripheral interconnect channels supporting a first communication protocol that is serial and a plurality of high data rate capable channels supporting a second communication protocol different than the first communication protocol; a hardware plane module with a first programmable logic device (PLD) that is a field programmable gate array (FPGA), the first PLD connected to the plurality of high data rate capable channels, and a plurality of near-memory accelerator modules connected to the first PLD, each of the near-memory accelerator modules having a second PLD, wherein the second PLD is connected to the first PLD and each of the second PLDs is connected to a peripheral interconnect switch with a predetermined number of peripheral interconnect lanes, each of the peripheral interconnect switches being connected to a near-memory module with the predetermined number of PCie lanes, wherein a bandwidth between the second PLD and the corresponding near-memory module is only within ten percent of a bandwidth between the second PLD and the first PLD. ### Claim 11 (depends on 10) The reconfigurable server of claim 10, wherein a connection between the first PLD and the plurality of second PLDs provides 100 GB/s of bandwidth. ### Claim 12 (depends on 10) The reconfigurable server of claim 10, wherein the hardware plane module comprises a connector array connected to the first PLD, the connector array comprising a plurality of connectors configured to be connected to external devices. ### Claim 13 (depends on 12) The reconfigurable server of claim 12, wherein the plurality of connectors provides a bandwidth of 100 GB/s to the external devices. ### Claim 14 (depends on 12) The reconfigurable server of claim 12, wherein each of the near-memory accelerator modules comprises a connector configured to be connected to an external device. ### Claim 15 (depends on 12) The reconfigurable server of claim 12, further comprising a peripheral interconnect expander module connected to a portion of the plurality of peripheral interconnect channels extending from the processor array, the peripheral interconnect expander module comprising a second peripheral interconnect switch that connects the portion of the plurality of peripheral interconnect channels from the processor array to peripheral interconnect channels extending between the second peripheral interconnect switch and the second PLDs in the plurality of near-memory accelerator modules. ### Claim 16 A server rack, comprising: main memory; a switch; and a plurality of servers connected to the switch, at least one of the servers being a reconfigurable server that comprises: a processor module with a processor array, the processor array connected to the main memory and having a plurality of peripheral interconnect channels supporting a first communication protocol that is serial and a plurality of high data rate capable channels supporting a second communication protocol different than the first communication protocol; a hardware plane module with a first programmable logic device (PLD) that is a field programmable gate array (FPGA), the first PLD connected to the plurality of high data rate capable channels, wherein the hardware plane module comprises a connector array connected to the first PLD, the connector array comprising a plurality of connectors configured to be connected to external devices, and a plurality of near-memory accelerator modules connected to the first PLD, each of the near-memory accelerator modules having a second PLD, wherein the second PLD is connected the first PLD and each of the second PLDs is connected to a peripheral interconnect switch with a predetermined number of peripheral interconnect lanes, each of the peripheral interconnect switches being connected to a near-memory module with the predetermined number of peripheral interconnect lanes, wherein a bandwidth between the second PLD and the corresponding near-memory module is only within ten percent of a bandwidth between the second PLD and the first PLD; wherein at least one of the other plurality of servers is connected to the hardware plane module via one of the plurality of connectors. ### Claim 17 (depends on 16) The server rack of claim 16, wherein each of the servers is configured like the at least one server. ### Claim 18 (depends on 16) The server rack of claim 16, wherein the at least one server further comprises a peripheral interconnect expander module connected to a portion of the plurality of peripheral interconnect channels extending from the processor array, the peripheral interconnect expander module comprising a second peripheral interconnect switch that connects the portion of the plurality of peripheral interconnect channels from the processor array to peripheral interconnect channels extending between the second peripheral interconnect switch and the second PLDs in the plurality of near-memory accelerator modules. ### Claim 19 (depends on 16) The server rack of claim 16, wherein the plurality of connectors collectively provide 100 GB/s of bandwidth. ### Claim 20 (depends on 16) The server rack of claim 16, wherein the peripheral interconnect channels comprise peripheral component interconnect express (PCIe) channels, and the high data rate capable channels comprise OPENCAPI channels.