# US 11,907,141 B1 · Flexible dual ranks memory system to boost performance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,141 B1 - Document ID: US11907141B1 - Status: Granted - Kind: B1 - Application number: 17/929,946 - Filed: 2022-09-06 - Published: 2024-03-07 - Granted: 2024-02-20 - Earliest claimed: 2022-09-06 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Jungwon Suh; Pankaj Deshmukh; Shyamkumar Thoziyoor; Subbarao Palacharla - Web page: https://patentgrep.com/patent/US11907141B1 ## CPC - G06F 13/1684: {using multiple buses} - G06F 13/1694: {Configuration of memory controller to different memory types} - G06F 12/0623: {for memory modules} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh} - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device. ## Claims ### Claim 1 A method implemented in a memory system, comprising: receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank; generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel; sending, from the memory controller, the first signal to the first memory device; generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel; and sending, from the memory controller, the second signal to the second memory device; and determining whether the first address at which to implement the first memory access command in the logical rank is at the logical rank, wherein generating the first signal, sending the first signal, generating the second signal, and sending the second signal occur in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank. ### Claim 2 (depends on 1) The method of claim 1, further comprising: generating, by the memory controller, a third signal configured to indicate to the first memory device to activate components of the first memory device associated with the first partial channel; sending, from the memory controller, the third signal to the first memory device; generating, by the memory controller, a fourth signal configured to indicate to the second memory device to activate components of the first memory device associated with the second partial channel; and sending, from the memory controller, the fourth signal to the second memory device. ### Claim 3 (depends on 1) The method of claim 1, further comprising: receiving, at the memory controller, a second memory access command and a second address at which to implement the second memory access command in a rank; generating, by the memory controller, a third signal configured to indicate to the first memory device of the rank to implement the second memory access command via the first partial channel; sending, from the memory controller, the third signal to the first memory device; generating, by the memory controller, a fourth signal configured to indicate to the first memory device of the rank to implement the second memory access command via the second partial channel; and sending, from the memory controller, the fourth signal to the first memory device. ### Claim 4 (depends on 3) The method of claim 3, further comprising determining whether the second address at which to implement the second memory access command in the rank is at the logical rank, wherein generating the third signal, sending the third signal, generating the fourth signal, and sending the fourth signal occur in response to determining that the second address at which to implement the second memory access command in the rank is not at the logical rank. ### Claim 5 (depends on 3) The method of claim 3, further comprising: receiving, at a first partial channel interface of the first memory device for the first partial channel, the first signal; implementing, via the first partial channel, the first memory access command at the first memory device; receiving, at a second partial channel interface of the second memory device for the second partial channel, the second signal; and implementing, via the second partial channel, the second memory access command at the second memory device. ### Claim 6 (depends on 5) The method of claim 5, wherein implementing the first memory access command at the first memory device and implementing the second memory access command at the second memory device comprise implementing the first memory access command at the first memory device and implementing the second memory access command at the second memory device in parallel. ### Claim 7 A computing device, comprising: a first memory device; a second memory device; and a memory controller communicatively connected to the first memory device and the second memory device, and configured to: receive a first memory access command and a first address at which to implement the first memory access command in a logical rank; generate a first signal configured to indicate to the first memory device of the logical rank to implement the first memory access command via a first partial channel; send the first signal to the first memory device; generate a second signal configured to indicate to the second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel; and send the second signal to the second memory device. ### Claim 8 (depends on 7) The computing device of claim 7, wherein the memory controller is further configured to: generate a third signal configured to indicate to the first memory device to activate components of the first memory device associated with the first partial channel; send the third signal to the first memory device; generate a fourth signal configured to indicate to the second memory device to activate components of the first memory device associated with the second partial channel; and send the fourth signal to the second memory device. ### Claim 9 (depends on 7) The computing device of claim 7, wherein the memory controller is further configured to: receive a second memory access command and a second address at which to implement the second memory access command in a rank; generate a third signal configured to indicate to the first memory device of the rank to implement the second memory access command via the first partial channel; send the third signal to the first memory device; generate a fourth signal configured to indicate to the first memory device of the rank to implement the second memory access command via the second partial channel; and send the fourth signal to the first memory device. ### Claim 10 (depends on 9) The computing device of claim 9, wherein the memory controller is further configured to: determine whether the second address at which to implement the second memory access command in the rank is at the logical rank; and generate the third signal, send the third signal, generate the fourth signal, and send the fourth signal in response to determining that the second address at which to implement the second memory access command in the rank is not at the logical rank. ### Claim 11 (depends on 9) The computing device of claim 9, wherein: the first memory device is configured to: receive, at a first partial channel interface of the first memory device for the first partial channel, the first signal; and implement, by the first partial channel, the first memory access command at the first memory device; and the second memory device is configured to: receive, at a second partial channel interface of the second memory device for the second partial channel, the second signal; and implement, by the second partial channel, the second memory access command at the second memory device. ### Claim 12 (depends on 11) The computing device of claim 11, wherein the first memory device is configured to implement the first memory access command at the first memory device in parallel with implementing the second memory access command at the second memory device. ### Claim 13 A computing device, comprising: means for receiving a first memory access command and a first address at which to implement the first memory access command in a logical rank; means for generating a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel; means for sending the first signal to the first memory device; means for generating a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel; means for sending the second signal to the second memory device; and means for determining whether the first address at which to implement the first memory access command in the logical rank is at the logical rank, wherein means for generating the first signal, means for sending the first signal, means for generating the second signal, and means for sending the second signal are implemented in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank. ### Claim 14 (depends on 13) The computing device of claim 13, further comprising: means for generating a third signal configured to indicate to the first memory device to activate components of the first memory device associated with the first partial channel; means for sending the third signal to the first memory device; means for generating a fourth signal configured to indicate to the second memory device to activate components of the first memory device associated with the second partial channel; and means for sending the fourth signal to the second memory device. ### Claim 15 (depends on 13) The computing device of claim 13, further comprising: means for receiving a second memory access command and a second address at which to implement the second memory access command in a rank; means for generating a third signal configured to indicate to the first memory device of the rank to implement the second memory access command via the first partial channel; means for sending the third signal to the first memory device; means for generating a fourth signal configured to indicate to the first memory device of the rank to implement the second memory access command via the second partial channel; and means for sending the fourth signal to the first memory device. ### Claim 16 (depends on 15) The computing device of claim 15, further comprising means for determining whether the second address at which to implement the second memory access command in the rank is at a logical rank, wherein means for generating the third signal, means for sending the third signal, means for generating the fourth signal, and means for sending the fourth signal are implemented in response to determining that the second address at which to implement the second memory access command in the rank is not at the logical rank. ### Claim 17 (depends on 15) The computing device of claim 15, further comprising: means for means for receiving the first signal; means for implementing the first memory access command at the first memory device via the first partial channel; means for receiving the second signal; and means for implementing the second memory access command at the second memory device via the second partial channel. ### Claim 18 (depends on 17) The computing device of claim 17, further comprising means for implementing the first memory access command at the first memory device and implementing the second memory access command at the second memory device in parallel. ### Claim 19 A memory controller configured to: receive a first memory access command and a first address at which to implement the first memory access command in a logical rank; generate a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel; send the first signal to the first memory device; generate a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel; and send the second signal to the second memory device; and determine whether the first address at which to implement the first memory access command in the logical rank is at the logical rank; and generate the first signal, sending the first signal, generate the second signal, and send the second signal occur in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank. ### Claim 20 (depends on 19) The memory controller of claim 19, wherein the memory controller is further configured to: generate a third signal configured to indicate to the first memory device to activate components of the first memory device associated with the first partial channel; send the third signal to the first memory device; generate a fourth signal configured to indicate to the second memory device to activate components of the first memory device associated with the second partial channel; send the fourth signal to the second memory device. ### Claim 21 (depends on 19) The memory controller of claim 19, wherein the memory controller is further configured to: receive a second memory access command and a second address at which to implement the second memory access command in a rank; generate a third signal configured to indicate to the first memory device of the rank to implement the second memory access command via the first partial channel; send the third signal to the first memory device; generate a fourth signal configured to indicate to the first memory device of the rank to implement the second memory access command via the second partial channel; and send the fourth signal to the first memory device. ### Claim 22 (depends on 21) The memory controller of claim 21, wherein the memory controller is further configured to: determine whether the second address at which to implement the second memory access command in the rank is at the logical rank; and generate the third signal, send the third signal, generate the fourth signal, and send the fourth signal in response to determining that the second address at which to implement the second memory access command in the rank is not at the logical rank. ### Claim 23 A method implemented in a memory system, comprising: receiving, at a first partial channel interface of a first memory device for a first partial channel, a first refresh signal; receiving, at a second partial channel interface of a second memory device for a second partial channel, a second refresh signal; implementing, via the first partial channel, a refresh operation at the first memory device in response to the first refresh signal; and implementing, via the second partial channel, a refresh operation at the second memory device in response to the second refresh signal. ### Claim 24 (depends on 23) The method of claim 23, wherein the first memory device and the second memory device are different memory devices of a logical rank, and implementing the refresh operation at the second memory device comprises implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device. ### Claim 25 (depends on 24) The method of claim 24, further comprising: receiving, at the first partial channel interface, a first signal configured to cause the first memory device of the logical rank to implement a first memory access command via the first partial channel; receiving, at the second partial channel interface, a second signal configured to cause the second memory device of the logical rank to implement a second memory access command via the second partial channel; implementing, via the first partial channel, the first memory access command at the first memory device following implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device; and implementing, via the second partial channel, the second memory access command at the second memory device following implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device. ### Claim 26 (depends on 23) The method of claim 23, wherein the second memory device is the first memory device, the method further comprising: waiting a designated refresh period for the refresh operation at the first memory device, wherein implementing the refresh operation at the second memory device comprises implementing the refresh operation at the second memory device following the designated refresh period. ### Claim 27 (depends on 25) The method of claim 25, further comprising: receiving, at the first partial channel interface, a first signal configured to cause the first memory device to implement a first memory access command via the first partial channel; receiving, at the second partial channel interface, a second signal configured to cause the second memory device to implement a second memory access command via the second partial channel; implementing, via the first partial channel, the first memory access command at the first memory device following implementing the refresh operation at the second memory device following the designated refresh period; and implementing, via the second partial channel, the second memory access command at the second memory device following implementing the refresh operation at the second memory device following the designated refresh period.