# US 11,907,140 B2 · Serial interface for semiconductor package

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- Number: US 11,907,140 B2
- Document ID: US11907140B2
- Status: Granted
- Kind: B2
- Application number: 17/699,942
- Filed: 2022-03-21
- Published: 2023-03-23
- Granted: 2024-02-20
- Earliest claimed: 2018-08-03
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Benjamin Kerr; Philip Rose; Robert Reed
- Web page: https://patentgrep.com/patent/US11907140B2

## CPC

- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 1/3243: {Power saving in microcontroller unit}
- G06F 13/4291: {using a clocked protocol}
- H04L 1/004: {by using forward error control (H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.

## Claims

### Claim 1

A system for serial communication, comprising:
a controller;
a semiconductor package comprising a semiconductor memory; and
a serial interface configured to connect the semiconductor memory to the controller,
wherein the serial interface is configured to transfer data between the controller and the semiconductor memory at a speed of transfer that is variable by employing a signaling protocol, and
wherein the serial interface is configured to transfer the data together with an encoded clock signal, the encoded clock signal having a rate associated with the variable speed of transfer of data, wherein the encoded clock signal is embedded together with the data in a transmitted signal.

### Claim 2 (depends on 1)

The system of claim 1, wherein the speed of transfer of the data is communicated by the controller to the semiconductor memory using the serial interface and the signaling protocol.

### Claim 3 (depends on 2)

The system of claim 2, wherein the serial interface is configured to implement a plurality of lanes using four pins per lane, and one of the plurality of lanes comprises the controller-to-package connection and the package-to-controller connection.

### Claim 4 (depends on 1)

The system of claim 1, wherein the serial interface comprises a controller-to-package connection and a package-to-controller connection.

### Claim 5 (depends on 1)

The system of claim 1, wherein the signaling protocol is one of LVDS and CML.

### Claim 6 (depends on 1)

The system of claim 1, wherein the controller is configured to selectively set the rate of the encoded clock signal to minimize power consumption.

### Claim 7 (depends on 1)

The system of claim 1, wherein the serial interface comprises a bridge device configured to serially connect to the controller, and wherein the semiconductor memory comprises a plurality of semiconductor die, and wherein the bride device is configured to connect to the plurality of semiconductor die in parallel, via at least one parallel bus connection.

### Claim 8 (depends on 7)

The system of claim 7, wherein the bridge device is configured to implement an error correction technique.

### Claim 9 (depends on 8)

The system of claim 8, wherein the bridge device is configured to reprogram the error correction technique based on instructions received from the controller.

### Claim 10 (depends on 7)

The system of claim 7, wherein the serial interface is included in the semiconductor package, and the semiconductor package comprises an encapsulation material that encapsulates the plurality of semiconductor die and encapsulates the bridge device.

### Claim 11 (depends on 7)

The system of claim 7, wherein the semiconductor package comprises an encapsulation material that encapsulates the plurality of semiconductor die, and the bridge device is disposed outside of the encapsulation material.

### Claim 12 (depends on 7)

The system of claim 7, wherein the serial interface includes:
a controller-to-package connection comprising a first pin and a second pin connected to the controller, and the controller-to-package connection is configured to transmit a differential signal to the controller using the first pin and the second pin; and
a package-to-controller connection comprising a third pin and a fourth pin connected to the controller, and the package-to-controller connection is configured to receive a differential signal from the controller using the third pin and the fourth pin.

### Claim 13 (depends on 1)

The system of claim 1, wherein the semiconductor memory comprises a plurality of semiconductor die, the system further comprising a plurality of serial interfaces including the serial interface, the plurality of serial interfaces respectively connecting the plurality of semiconductor die to the controller.

### Claim 14

A semiconductor package, comprising:
a flash memory; and
a bridge device comprising a high-speed serial interface connected to an external controller and a parallel interface connected to the flash memory,
wherein the high-speed serial interface is configured to transfer data between the external controller and the flash memory at a speed of transfer that is variable by employing a signaling protocol, and
wherein the high-speed serial interface is configured to transfer the data together with an encoded clock signal, the encoded clock signal having a rate associated with the variable speed of transfer of data, wherein the encoded clock signal is embedded together with the data in a transmitted signal.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the bridge device is configured to implement an error correction technique according to error correction firmware accessible to the bridge device.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the bridge device is configured to reprogram the error correction firmware based on instructions received from the controller.

### Claim 17 (depends on 14)

The semiconductor package of claim 14, wherein the bridge device comprises a controller configured to determine a device identification included in a first communication received via the high-speed serial interface, and configured to responsively transmit, based on the device identification, a second communication to the flash memory via the parallel interface.

### Claim 18

A method for communication for a semiconductor package comprising a package controller, a serial interface, and a parallel interface, the method comprising:
receiving, by the serial interface from an external controller, a first communication comprising device identity information, the first communication configured to transfer data between the external controller and the semiconductor package at a speed of transfer that is variable according to a signaling protocol, wherein the serial interface is configured to transfer the data together with an encoded clock signal, the encoded clock signal having a rate associated with the variable speed of transfer of data, wherein the encoded clock signal is embedded together with the data in a transmitted signal;
identifying, by the package controller, a first semiconductor die based on the device identity information;
routing, by the package controller, a second communication to the first semiconductor die via the parallel interface;
receiving, by the package controller from the first semiconductor die, via the parallel interface, a third communication; and
transmitting, by the package controller to the external controller via the serial interface using the signaling protocol that includes the encoded clock signal, a fourth communication based on the third communication.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first communication is a command to perform an operation, and wherein the third communication indicates that the operation was implemented.

### Claim 20 (depends on 19)

The method of claim 19, wherein the device identity information of the first communication specifies the first semiconductor die and a second semiconductor die, and further comprising:
receiving, by the package controller from the second semiconductor die, via the parallel interface, a fifth communication; and
transmitting, by the package controller to the external controller via the serial interface, a sixth communication based on the fifth communication.

### Claim 21 (depends on 20)

The method of claim 20, wherein the sixth communication is transmitted asynchronously with the fourth communication.

### Claim 22 (depends on 18)

The method of claim 18, further comprising generating, by the package controller, the fourth communication responsive to receiving the third communication, and storing the fourth communication in a buffer for transmission to the external controller.

### Claim 23 (depends on 18)

The method of claim 18, further comprising configuring, by the external controller, the rate of the encoded clock signal to minimize power consumption.