# US 11,907,139 B2 · Memory system design using buffer(s) on a mother board

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- Number: US 11,907,139 B2
- Document ID: US11907139B2
- Status: Granted
- Kind: B2
- Application number: 18/085,481
- Filed: 2022-12-20
- Published: 2023-07-27
- Granted: 2024-02-20
- Earliest claimed: 2015-06-09
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Chi-Ming Yeung; Yoshie Nakabayashi; Thomas Giovannini; Henry Stracovsky
- Web page: https://patentgrep.com/patent/US11907139B2

## CPC

- G06F 13/1673: {using buffers}
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/4068: {Electrical coupling}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

## Claims

### Claim 1

A system comprising:
a central processing unit (CPU);
at least one dual in-line memory module (DIMM) comprising a first rank of one or more memory devices and a second rank of one or more memory devices;
a data buffer integrated circuit (IC);
a first data path coupled between the CPU and the data buffer IC;
a second data path coupled between the data buffer IC and a first data buffer device within the at least one DIMM, wherein the first data buffer device is coupled to the first rank of the one or more memory devices via the second data path; and
a third data path coupled between the data buffer IC and a second data buffer device within the at least one DIMM, wherein the second data buffer device is coupled to the second rank of the one or more memory devices via the third data path.

### Claim 2 (depends on 1)

The system of claim 1, wherein the at least one DIMM is to receive a first set of control signals directed to the first rank and a second set of control signals directed to the second rank.

### Claim 3 (depends on 1)

The system of claim 1, further comprising:
a second data buffer IC;
a second DIMM comprising a third rank of one or more memory devices and a fourth rank of one or more memory devices;
a fourth data path coupled between the second data buffer IC and the third rank of the one or more memory devices; and
a fifth data path coupled between the second data buffer IC and the fourth rank of the one or more memory device.

### Claim 4 (depends on 3)

The system of claim 3, wherein the data buffer IC and the second data buffer IC are coupled to the CPU in parallel.

### Claim 5 (depends on 1)

The system of claim 1, further comprising:
a second DIMM comprising a third rank of one or more memory devices and a fourth rank of one or more memory devices, wherein the at least one DIMM and the second DIMM are coupled in parallel to the data buffer IC.

### Claim 6 (depends on 1)

The system of claim 1, wherein the CPU comprises a memory controller coupled to an address buffer device disposed on the at least one DIMM.

### Claim 7 (depends on 1)

The system of claim 1, further comprising an address buffer IC coupled to the CPU and the at least one DIMM.

### Claim 8 (depends on 1)

The system of claim 1, further comprising an address buffer IC coupled to the CPU and an address buffer device disposed on the at least one DIMM.

### Claim 9 (depends on 1)

The system of claim 1, further comprising a bus coupled between the CPU and the at least one DIMM, wherein the CPU is to send an alert signal to the at least one DIMM over the bus.

### Claim 10

A system comprising:
a processor comprising a memory controller;
a first data buffer device;
a first memory channel coupled between the processor and the first data buffer device; and
a dual in-line memory module (DIMM) coupled to the first data buffer device via a second memory channel and a third memory channel, wherein the DIMM comprises a second data buffer device coupled to the first data buffer device via the second memory channel and a third data buffer device coupled to the first data buffer device via the second memory channel, wherein the second data buffer device is to access a first rank of one or more memory devices of the DIMM via the second memory channel and the third data buffer device is to access a second rank of one or more memory devices of the DIMM via the third memory channel.

### Claim 11 (depends on 10)

The system of claim 10, wherein the processor and the first data buffer device are disposed on a circuit board comprising a memory slot in which the DIMM is inserted.

### Claim 12 (depends on 10)

The system of claim 10, wherein the DIMM is to receive a first set of control signals directed to the first rank and a second set of control signals directed to the second rank.

### Claim 13 (depends on 10)

The system of claim 10, further comprising:
a fourth data buffer device; and
a second DIMM coupled to the fourth data buffer device via a third memory channel and a fourth memory channel, wherein the second DIMM comprises a third rank of one or more memory devices and a fourth rank of one or more memory devices, wherein the second data buffer device is to access the third rank of the one or more memory devices via the third memory channel and access the fourth rank of the one or more memory devices via the fourth memory channel.

### Claim 14 (depends on 13)

The system of claim 13, wherein the first data buffer device and the fourth data buffer device are coupled to the processor in parallel.

### Claim 15 (depends on 13)

The system of claim 13, wherein the first data buffer device and the fourth data buffer device are part of a data buffer integrated circuit (IC).

### Claim 16 (depends on 10)

The system of claim 10, further comprising:
a second DIMM comprising a third rank of one or more memory devices and a fourth rank of one or more memory devices, wherein the DIMM and the second DIMM are coupled in parallel to the first data buffer device.

### Claim 17 (depends on 10)

The system of claim 10, wherein the memory controller is coupled to an address buffer device disposed on the DIMM.

### Claim 18

A system comprising:
a central processing unit (CPU);
at least one dual in-line memory module (DIMM) comprising a first data buffer device coupled to a first rank of one or more memory devices and a second data buffer device coupled to a second rank of one or more memory devices; and
means for accessing the first rank of the one or more memory devices via a first memory channel;
means for accessing the second rank of the one or more memory devices via a second memory channel; and
means for sending or receiving data between the CPU and the DIMM via a third memory channel.