# US 11,907,136 B2 · Apparatuses, systems, and methods for invalidating expired memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,907,136 B2
- Document ID: US11907136B2
- Status: Granted
- Kind: B2
- Application number: 16/820,630
- Filed: 2020-03-16
- Published: 2020-07-09
- Granted: 2024-02-20
- Earliest claimed: 2020-03-16
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ginger H. Gilsdorf; Karthik Kumar; Mark A. Schmisseur; Thomas Willhalm; Francesc Guim Bernat
- Web page: https://patentgrep.com/patent/US11907136B2

## CPC

- G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
- G06F 1/14: Time supervision arrangements, e.g. real time clock
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0891: using clearing, invalidating or resetting means
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles}
- G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically}
- G06F 2212/1024: Latency reduction
- G11C 13/0061: {Timing circuits or methods}
- G11C 16/32: Timing circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.

## Claims

### Claim 1

An apparatus, comprising:
a memory device including memory locations; and
hardware logic coupled to the memory device to:
identify a table that includes indications of a plurality of memory ranges, indications of a plurality of temporal ranges, and indications of a plurality of data invalidation techniques, wherein:
respective ones of the plurality of temporal ranges and respective ones of the plurality of data invalidation techniques correspond to respective ones of the plurality of memory ranges;
respective memory ranges are an address range that correspond to a plurality of the memory locations in the memory device; and
respective temporal ranges are a time range during which data stored in the respective memory ranges is valid according to a data aging policy;
identify, based on an identification that a time value is outside of a temporal range of the plurality of temporal ranges, that the data in a corresponding memory range of the plurality of memory ranges is expired; and
invalidate, based on a data invalidation technique that corresponds to the temporal range and the memory range, the expired data in the memory range.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the time value is a current time and further comprising a timer or clock coupled to provide the current time to the hardware logic.

### Claim 3 (depends on 2)

The apparatus of claim 2, further comprising a battery source coupled to the timer or clock to provide power to the timer or clock when a power supply from a platform is absent.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the apparatus is a dual-in-line-memory module (DIMM) and the hardware logic resides on the DIMM with the memory device.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the interface is a memory controller interface and the hardware logic is to invalidate the data when the DIMM is decoupled from the interface.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the apparatus is a memory drive.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the temporal range is a time-to-live (TTL) value and when the TTL value is expired, the data in the corresponding memory range is identified as expired.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the plurality of invalidation techniques includes marking the memory range as expired, clearing or deleting an encryption key, and writing zeros into a data location of the memory locations.

### Claim 9

A method, comprising:
identifying a table that includes indications of a plurality of memory ranges, indications of a plurality of temporal ranges, and indications of a plurality of data invalidation techniques, wherein:
respective ones of the plurality of temporal ranges and respective ones of the plurality of data invalidation techniques correspond to respective ones of the plurality of memory ranges;
respective memory ranges are an address range that correspond to a plurality of the memory locations in the memory device; and
respective temporal ranges are a time range during which data stored in the respective memory ranges is valid according to a data aging policy;
identifying, based on an identification that a time value is outside of a temporal range of the plurality of temporal ranges, that the data in a corresponding memory range of the plurality of memory ranges is expired; and
invalidating, based on a data invalidation technique that corresponds to the temporal range and the memory range, the expired data in the memory range.

### Claim 10 (depends on 9)

The method of claim 9, wherein invalidating by the hardware logic, the data that is expired in the memory device includes invalidating the data when the memory device is decoupled from a platform interface.

### Claim 11 (depends on 9)

The method of claim 9, wherein checking, by the hardware logic, the temporal range includes checking a timer or clock to determine if a time-to-live (TTL) value is expired or exceeded.

### Claim 12 (depends on 11)

The method of claim 11, wherein the timer or clock is implemented without an option to be reset.

### Claim 13

A system, comprising:
a processor;
a memory device coupled to the processor, wherein the memory device includes a plurality of memory locations; and
hardware logic coupled to the memory device to:
identify a table that includes indications of a plurality of memory ranges, indications of a plurality of temporal ranges, and indications of a plurality of data invalidation techniques, wherein:
respective ones of the plurality of temporal ranges and respective ones of the plurality of data invalidation techniques correspond to respective ones of the plurality of memory ranges;
respective memory ranges are an address range that correspond to a plurality of the memory locations in the memory device; and
respective temporal ranges are a time range during which data stored in the respective memory ranges is valid according to a data aging policy;
identify, based on an identification that a time value is outside of a temporal range of the plurality of temporal ranges, that the data in a corresponding memory range of the plurality of memory ranges is expired; and
invalidate, based on a data invalidation technique that corresponds to the temporal range and the memory range, the expired data in the memory range.

### Claim 14 (depends on 13)

The system of claim 13, wherein the temporal range includes a time-to-live (TTL) value.

### Claim 15 (depends on 13)

The system of claim 13, wherein the memory device and the hardware logic are located on a memory module to be decoupled from the processor.

### Claim 16 (depends on 15)

The system of claim 15, wherein the memory module is a dual-in-line-memory module (DIMM).

### Claim 17 (depends on 16)

The system of claim 16, further comprising a battery source and a timer coupled to the hardware logic on the DIMM and wherein the battery source is to provide power to the timer when a power supply from the system is absent.

### Claim 18 (depends on 13)

The system of claim 13, wherein a timer to provide the time value is implemented without an option to be reset.

### Claim 19 (depends on 13)

The system of claim 13, wherein the memory device is included in a memory drive or is embedded memory included on the processor.

### Claim 20 (depends on 13)

The system of claim 13, wherein to invalidate the data includes to mark the memory range as expired, delete a memory range encryption key, or forcibly zero memory locations of the data.