# US 11,907,134 B1 · Nonvolatile memory controller supporting variable configurability and forward compatibility > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,134 B1 - Document ID: US11907134B1 - Status: Granted - Kind: B1 - Application number: 17/469,758 - Filed: 2021-09-08 - Granted: 2024-02-20 - Earliest claimed: 2014-09-09 - Assignees: Radian Memory Systems, Inc. - Applicants: Radian Memory Systems, Inc. - Inventors: Robert Lercari; Alan Chen; Mike Jadon; Craig Robertson; Andrey V. Kuzmin - Web page: https://patentgrep.com/patent/US11907134B1 ## CPC - G06F 12/1009: using page tables, e.g. page table structures - G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]} - G06F 3/064: {Management of blocks} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 12/0207: {with multidimensional access, e.g. row/column, matrix} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0662: {Virtualisation aspects} - G06F 2212/1016: Performance improvement - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7202: Allocation control and policies - G06F 2212/7205: Cleaning, compaction, garbage collection, erase control - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client. ## Claims ### Claim 1 A memory controller to control nonvolatile memory, the memory controller comprising: circuitry to map host-provided addresses to physical addresses in the nonvolatile memory according to one of two alternate mappings; and a register to store a programmably-defined address mapping parameter; wherein the circuitry is to map data, received with sequentially-received write requests, to a number of respective storage units of a type of storage unit, wherein the type is a same one from a group of channels, dies, erase units, planes, and pages, wherein the number of the respective storage units of the type is variable dependent on a value of the programmably-defined address mapping parameter; wherein each host-provided address comprises a first portion and a second portion, and for a first one of the two alternate mappings, the first portion of each host-provided address is mapped to a first number of first storage units of the nonvolatile memory and the second portion of each host-provided address is mapped to a first number of second storage units of the nonvolatile memory, for a second one of the two alternate mappings, the first portion of each host-provided address is mapped by said circuitry to a second number of the first storage units and the second portion of each host-provided address is mapped by said circuitry to a second number of the second storage units; the first storage units are respective units of a first type of units from the group, and the second storage units are respective units of a second type of units from the group, and one of the first portion and the second portion can be mapped to a non-power of two set of structural addresses and the circuitry to map is to perform modulo arithmetic on each host-provided address to recover the other of the first portion and the second portion, with no address in a range of addresses represented by the first portion and the second portion remaining unmapped to a storage location in the nonvolatile memory; and circuitry to service the write requests by issuing commands accompanied by the physical addresses, the physical addresses being generated using the one of the two alternate mappings. ### Claim 2 (depends on 1) The memory controller of claim 1 wherein: each host-provided address comprises a third portion; the circuitry to map is configured to map the third portion to a third type of storage units from the group, according to a value conveyed by the third portion; and each of the physical addresses is dependent on said mapping of the third portion. ### Claim 3 (depends on 1) The memory controller of claim 1 wherein the nonvolatile memory comprises flash memory dies and wherein the circuitry to map is configured, dependent on a register value, to map one of the first portion and the second portion to a die address which designates one of the flash memory dies. ### Claim 4 (depends on 1) The memory controller of claim 1 wherein: the circuitry to map is configured to identify two or more virtual storage structures mapped to storage in the nonvolatile memory; the host-provided addresses are first host-provided addresses, the circuitry to map is configured to map the first host-provided addresses to a first one of the two or more virtual storage structures; the circuitry to map is configured to map second host-provided addresses to a second one of the two or more virtual storage structures, to a respective set of the first storage units and a respective set of the second storage units; and the mapping for the second host-provided addresses can be different from the one of the two alternative mappings for the first host-provided addresses, in a manner such that each of the first host-provided addresses and the second host-provided addresses map to different, respective ratios of the first storage units to the second storage units for the respective virtual storage structure. ### Claim 5 (depends on 1) The memory controller of claim 1 wherein: the circuitry to map is configured to perform address translation for at least a portion of each host-provided address by identifying a selected one of plural address translation tables according to one of the first portion and the second portion, by identifying a value of a remainder portion of the provided host-provided address, and by looking up a corresponding one of the physical addresses indexed by the selected one of the plural address translation table to the value of the remainder portion; and the circuitry to service the write requests is configured to issue one or more read commands to the nonvolatile memory responsive to the one of the read requests in a manner that specifies the corresponding one of the physical addresses. ### Claim 6 (depends on 1) The memory controller of claim 1 wherein the circuitry to map is configured such that: for a first value of the programmably-defined address mapping parameter, the memory controller maps data accompanying the respective sequentially-received write requests to a first number, greater than one, of the respective storage units; and for a second value of the programmably-defined address mapping parameter, the memory controller maps the respective sequentially-received write requests to a second number, greater than one, of the respective storage units. ### Claim 7 (depends on 1) The memory controller of claim 1 wherein the programmably-defined address mapping parameter comprises one of: a number of pages within a same erase unit to which respective ones of the respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is to be also directed to the number of pages; a number of erase units within a same die to which respective ones of respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is to be also directed to the number of erase units; and a number of dies to which respective ones of the respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is to be also directed to the number of dies. ### Claim 8 (depends on 1) The memory controller of claim 1 wherein the first portion corresponds to one of a virtual channel, a virtual die, a virtual erase unit, a virtual plane, and a virtual page, and maps exclusively to at least one corresponding physical storage unit, such that a virtual channel maps to at least one physical channel, such that a virtual die maps on to at least one physical die, such that a virtual erase unit maps on to at least one physical erase unit, such that a virtual plane maps on to at least one physical plane, and such that a virtual page maps on to at least one physical page. ### Claim 9 (depends on 1) The memory controller of claim 1 wherein the memory controller is embodied as an integrated circuit. ### Claim 10 A memory system comprising: nonvolatile memory; circuitry to map host-provided addresses to physical addresses in the nonvolatile memory according to one of two alternate mappings; and a register to store a programmably-defined address mapping parameter; wherein the circuitry is to map data, received with sequentially-received write requests, to a number of respective storage units of a type of storage unit, wherein the type is a same one from a group of channels, dies, erase units, planes, and pages, wherein the number of the respective storage units of the type is variable dependent on a value of the programmably-defined address mapping parameter; wherein each host-provided address comprises a first portion and a second portion, and for a first one of the two alternate mappings, the first portion of each host-provided address is mapped to a first number of first storage units of the nonvolatile memory and the second portion of each host-provided address is mapped to a first number of second storage units of the nonvolatile memory; for a second one of the two alternate mappings, the first portion of each host-provided address is mapped by said circuitry to a second number of the first storage units and the second portion of each host-provided address is mapped by said circuitry to a second number of the second storage units; the first storage units are respective units of a first type of units from the group, and the second storage units are respective units of a second type of units from the group, and one of the first portion and the second portion can be mapped to a non-power of two set of structural addresses and the circuitry to map is to perform modulo arithmetic on each host-provided address to recover the other of the first portion and the second portion, with no address in a range of addresses represented by the first portion and the second portion remaining unmapped to a storage location in the nonvolatile memory; and circuitry to service the write requests by issuing commands accompanied by the physical addresses, the physical addresses being generated using the selective one of the two alternate mappings. ### Claim 11 (depends on 10) The memory system of claim 10 wherein: each host-provided address comprises a third portion; the circuitry to map is configured to map the third portion to a third type of storage units from the group, according to a value conveyed by the third portion; and each of the physical addresses is dependent on said mapping of the third portion. ### Claim 12 (depends on 10) The memory system of claim 10 wherein the nonvolatile memory comprises flash memory dies and wherein the circuitry to map is configured, dependent on a register value, to map one of the first portion and the second portion to a die address which designates one of the flash memory dies. ### Claim 13 (depends on 10) The memory system of claim 10 wherein: the circuitry to map is configured to identify two or more virtual storage structures mapped to storage in the nonvolatile memory; the host-provided addresses are first host-provided addresses, the circuitry to map is configured to map the first host-provided addresses to a first one of the two or more virtual storage structures; the circuitry to map is configured to map second host-provided addresses to a second one of the two or more virtual storage structures, to a respective set of the first storage units and a respective set of the second storage units; and the mapping for the second host-provided addresses can be different from the one of the two alternative mappings for the first host-provided addresses, in a manner such that each of the first host-provided addresses and the second host-provided addresses map to different, respective ratios of the first storage units to the second storage units for the respective virtual storage structure. ### Claim 14 (depends on 10) The memory system of claim 10 wherein: the circuitry to map is configured to perform address translation for at least a portion of each host-provided address by identifying a selected one of plural address translation tables according to one of the first portion and the second portion, by identifying a value of a remainder portion of the provided host-provided address, and by looking up a corresponding one of the physical addresses indexed by the selected one of the plural address translation table to the value of the remainder portion; and the circuitry to service the write requests is configured to issue one or more read commands to the nonvolatile memory responsive to the one of the read requests in a manner that specifies the corresponding one of the physical addresses. ### Claim 15 (depends on 10) The memory system of claim 10 wherein the circuitry to map is configured such that: for a first value of the programmably-defined address mapping parameter, the memory system maps data accompanying the respective sequentially-received write requests to a first number of the respective storage units; and for a second value of the programmably-defined address mapping parameter, the memory system maps the respective sequentially-received write requests to the respective storage units. ### Claim 16 (depends on 10) The memory system of claim 10 wherein the programmably-defined address mapping parameter comprises one of: a number of pages within a same erase unit to which respective ones of the respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is also directed to the number of pages; a number of erase units within a same die to which the respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is also directed to the number of pages; and a number of dies to which respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is also directed to the number of dies. ### Claim 17 (depends on 10) The memory system of claim 10 wherein the first portion corresponds to one of a virtual channel, a virtual die, a virtual erase unit, a virtual plane, and a virtual page, and maps to at least one corresponding physical storage unit, such that a virtual channel maps to at least one physical channel, such that a virtual die maps to at least one physical die, such that a virtual erase unit maps to at least one physical erase unit, such that a virtual plane maps to at least one physical plane, and such that a virtual page maps to at least one physical page. ### Claim 18 (depends on 10) The memory system of claim 10 wherein said memory system is embodied as a solid state drive (SSD).