# US 11,907,124 B2 · Using a shadow copy of a cache in a cache hierarchy

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- Number: US 11,907,124 B2
- Document ID: US11907124B2
- Status: Granted
- Kind: B2
- Application number: 17/709,807
- Filed: 2022-03-31
- Published: 2023-10-05
- Granted: 2024-02-20
- Earliest claimed: 2022-03-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Yair Fried; Aaron Tsai; Eyal Naor; Christian Jacobi; Timothy Bronson; Chung-Lung K. Shum
- Web page: https://patentgrep.com/patent/US11907124B2

## CPC

- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 2212/1024: Latency reduction
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/286: Mirrored cache memory
- G06F 2212/311: In host system
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

## Claims

### Claim 1

A computer-implemented process comprising:
maintaining a shadow copy of a level one (L1) cache in a cache hierarchy, the maintaining comprising:
updating the shadow copy of the L1 cache with memory content changes to the L1 cache a predetermined fixed number of pipeline cycles after the L1 cache is updated with the memory content changes, wherein the predetermined fixed number of pipeline cycles is one of two, four, eight, ten, and twenty pipeline cycles.

### Claim 2 (depends on 1)

The computer-implemented process of claim 1, further comprising updating an upstream cache in the cache hierarchy with content of the shadow copy of the L1 cache.

### Claim 3 (depends on 2)

The computer-implemented process of claim 2, wherein an error detection and correction scheme employed in the upstream cache detects and corrects larger errors than a scheme employed in the L1 cache.

### Claim 4 (depends on 2)

The computer-implemented process of claim 2, wherein the upstream cache implements a redundant array of independent memory (RAIM) based protection scheme, and the updating an upstream cache comprises:
selecting a cache line from the shadow copy of the L1 cache, the selected cache line comprising unchanged content and updated content;
calculating a new RAIM payload based on contents of the cache line;
sending the new RAIM payload and at least the changed content to the upstream cache; and
storing the new RAIM payload and the at least the changed content into the upstream cache.

### Claim 5 (depends on 2)

The computer-implemented process of claim 2, wherein the updating an upstream cache is performed at its access granularity without first reading from the upstream cache for any unchanged content to merge with the memory content changes.

### Claim 6 (depends on 2)

The computer-implemented process of claim 2, wherein a frequency of the updating an upstream cache is based on one or more programmable factors.

### Claim 7 (depends on 1)

The computer-implemented process of claim 1, wherein the updating comprises invalidating a cache line from the shadow copy of the L1 cache a number of pipeline cycles after invalidating the cache line from the L1 cache.

### Claim 8 (depends on 1)

The computer-implemented process of claim 1, wherein the shadow copy of the L1 cache implements an error correction code (ECC) based protection scheme.

### Claim 9 (depends on 1)

The computer-implemented process of claim 1, wherein the shadow copy of the L1 cache is used as a store gathering buffer.

### Claim 10

A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
maintaining a shadow copy of a level one (L1) cache in a cache hierarchy, the maintaining comprising:
updating the shadow copy of the L1 cache with memory content changes to the L1 cache a predetermined fixed number of pipeline cycles after the L1 cache is updated with the memory content changes, wherein the predetermined fixed number of pipeline cycles is one of two, four, eight, ten, and twenty pipeline cycles.

### Claim 11 (depends on 10)

The system of claim 10, wherein the operations further comprise updating an upstream cache in the cache hierarchy with content of the shadow copy of the L1 cache.

### Claim 12 (depends on 11)

The system of claim 11, wherein an error detection and correction scheme employed in the upstream cache detects and corrects larger errors than a scheme employed in the L1 cache.

### Claim 13 (depends on 11)

The system of claim 11, wherein the upstream cache implements a redundant array of independent memory (RAIM) based protection scheme, and the updating an upstream cache comprises:
selecting a cache line from the shadow copy of the L1 cache, the selected cache line comprising unchanged content and updated content;
calculating a new RAIM payload based on contents of the cache line;
sending the new RAIM payload and at least the changed content to the upstream cache; and
storing the new RAIM payload and the at least the changed content into the upstream cache.

### Claim 14 (depends on 11)

The system of claim 11, wherein the updating an upstream cache is performed at its access granularity without first reading from the upstream cache for any unchanged content to merge with the memory content changes.

### Claim 15 (depends on 10)

The system of claim 10, wherein the updating comprises invalidating a cache line from the shadow copy of the L1 cache a number of pipeline cycles after invalidating the cache line from the L1 cache.

### Claim 16 (depends on 10)

The system of claim 10, wherein the shadow copy of the L1 cache implements an error correction code (ECC) based protection scheme.

### Claim 17 (depends on 10)

The system of claim 10, wherein the shadow copy of the L1 cache is used as a store gathering buffer.

### Claim 18

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
maintaining a shadow copy of a level one (L1) cache in a cache hierarchy, the maintaining comprising:
updating the shadow copy of the L1 cache with memory content changes to the L1 cache a predetermined fixed number of pipeline cycles after the L1 cache is updated with the memory content changes, wherein the predetermined fixed number of pipeline cycles is one of two, four, eight, ten, and twenty pipeline cycles.

### Claim 19 (depends on 18)

The computer program product of claim 18, wherein the operations further comprise updating an upstream cache in the cache hierarchy with content of the shadow copy of the L1 cache.