# US 11,907,064 B2 · Memory controller and memory system including the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,907,064 B2
- Document ID: US11907064B2
- Status: Granted
- Kind: B2
- Application number: 17/697,530
- Filed: 2022-03-17
- Published: 2023-03-09
- Granted: 2024-02-20
- Earliest claimed: 2021-09-08
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ho-Youn Kim; Su Hun Lim
- Web page: https://patentgrep.com/patent/US11907064B2

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing}
- G06N 3/04: Architecture, e.g. interconnection topology
- G06N 3/063: using electronic means
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory controller includes a fault predictor which predicts a fault which causes an error occurring in a memory device, an error correction code (ECC) manager which classifies a type of the fault based on the predicted fault, and a plurality of ECC engines which perform ECC in parallel depending on the classified type of the faults. The fault predictor includes a memory error profiler which receives raw data related to the error and processes the raw data into an error profile that is data available for machine learning, and a memory fault prediction network which receives the error profile as an input, performs the machine learning using the error profile, and predicts the fault which causes the error.

## Claims

### Claim 1

A memory controller, comprising:
a fault predictor which predicts a fault which causes an error occurring in a memory device;
an ECC manager which classifies a type of the fault based on the predicted fault; and
a plurality of ECC engines which perform ECC in parallel depending on the classified type of the fault,
wherein the fault predictor includes
a memory error profiler which receives raw data related to the error and processes the raw data into an error profile that is data available for machine learning, and
a memory fault prediction network which receives the error profile as an input, performs the machine learning using the error profile, and predicts the fault which causes the error.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein the memory error profiler includes
an error profile precoder,
an error information utilizing block including a plurality of error information utilizing modules, and
an error profile generator which processes the data generated through the error information utilizing block into the error profile, and
wherein the error profile precoder precodes the raw data to be available for at least one of the plurality of error information utilizing modules.

### Claim 3 (depends on 2)

The memory controller of claim 2, wherein at least one of the plurality of error information utilizing modules is a TTF (Time-To-Failure) and TBE (Time Bet Error) calculation module.

### Claim 4 (depends on 2)

The memory controller of claim 2, wherein at least one of the plurality of error information utilizing modules is an ECC decoder utilizing module.

### Claim 5 (depends on 2)

The memory controller of claim 2, wherein at least one of the plurality of error information utilizing modules is an ECC address calculation module.

### Claim 6 (depends on 2)

The memory controller of claim 2, wherein at least one of the plurality of error information utilizing modules is an error count utilizing module.

### Claim 7 (depends on 1)

The memory controller of claim 1, wherein the ECC manager receives the predicted fault and transmits the predicted fault to a first ECC engine among the plurality of ECC engines, and
the first ECC engine performs ECC based on the predicted fault.

### Claim 8 (depends on 7)

The memory controller of claim 7, wherein the first ECC engine performs error scrubbing.

### Claim 9 (depends on 1)

The memory controller of claim 1, wherein the memory fault prediction network predicts the fault, using a CNN(Convolution Neural Network).

### Claim 10

A memory device, comprising:
a memory cell array which includes a plurality of memory cells for storing data; and
a memory controller which controls an access to the memory cell array,
wherein the memory controller includes
a fault predictor which includes a memory error profiler that receives raw data related to an error occurring in the data and processes the raw data into an error profile that is data available for machine learning, and a memory fault prediction network that receives the error profile as an input and performs the machine learning using the error profile to predict a fault that causes the error, and
an ECC manager which classifies a type of the fault based on the predicted fault.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the memory error profiler includes
an error profile precoder,
an error information utilizing block including a plurality of error information utilizing modules, and
an error profile generator which processes data generated through the error information utilizing block into the error profile, and
the error profile precoder precodes the raw data to be available for at least one of the plurality of error information utilizing modules.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein at least one of the plurality of error information utilizing modules is a TTF (Time-To-Failure) and TBE (Time Bet Error) calculation module, an ECC decoder utilizing module, an ECC address calculation module or an error count utilizing module.

### Claim 13 (depends on 10)

The memory device of claim 10, wherein the ECC manager receives the predicted fault and transmits the predicted fault to a first ECC engine among a plurality of ECC engines, and
the first ECC engine performs ECC based on the predicted fault.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the first ECC engine performs error scrubbing.

### Claim 15 (depends on 10)

The memory controller of claim 10, wherein the memory fault prediction network predicts the fault, using a CNN(Convolution Neural Network).

### Claim 16

A memory system, comprising:
a memory device which includes a memory cell array including a plurality of memory cells for storing data; and
a memory controller which includes a fault predictor that predicts a fault that causes an error occurring in the memory device, an ECC manager that classifies a type of the fault based on the predicted fault, and a plurality of ECC engines that perform ECC in parallel depending on the classified type of the fault,
wherein the fault predictor includes
a memory error profiler that receives raw data related to an error occurring in the data and processes the raw data into an error profile that is data available for machine learning, and
a memory fault prediction network that receives the error profile as an input and performs the machine learning using the error profile to predict a fault that causes the error.

### Claim 17 (depends on 16)

The memory system of claim 16, wherein the memory error profiler includes
an error profile precoder,
an error information utilizing block including a plurality of error information utilizing modules, and
an error profile generator which processes the data generated through the error information utilizing block into the error profile, and
the error profile precoder precodes the raw data to be available for at least one of the plurality of error information utilizing modules.

### Claim 18 (depends on 17)

The memory system of claim 17, wherein the ECC manager receives the predicted fault and transmits the predicted fault to a first ECC engine among the plurality of ECC engines, and
the first ECC engine performs ECC based on the predicted fault.

### Claim 19 (depends on 18)

The memory system of claim 18, wherein the first ECC engine performs error scrubbing.

### Claim 20 (depends on 16)

The memory controller of claim 16, wherein the memory fault prediction network predicts the fault, using a CNN(Convolution Neural Network).