# US 11,907,040 B2 · Memory power management method and processor system

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- Number: US 11,907,040 B2
- Document ID: US11907040B2
- Status: Granted
- Kind: B2
- Application number: 17/303,908
- Filed: 2021-06-10
- Published: 2022-02-03
- Granted: 2024-02-20
- Earliest claimed: 2021-06-10
- Assignees: NXP USA, Inc.
- Applicants: NXP USA, Inc.
- Inventors: Doru Cristian Gucea; Teodor Cosmin Grumei; Andrei Istodorescu
- Web page: https://patentgrep.com/patent/US11907040B2

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 12/023: {Free address space management}
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 8/75: Structural analysis for program understanding
- G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence)
- H04L 63/0442: {wherein the sending and receiving network entities apply asymmetric encryption, i.e. different keys for encryption and decryption (cryptographic mechanisms or cryptographic arrangements for public-key encryption H04L9/30)}
- H04L 63/166: {at the transport layer}
- G06F 2212/1028: Power efficiency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The processor system includes a processor coupled to a memory having a plurality of memory banks and a region configurable as a heap region. At least one memory bank is allocated to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation. At least one further memory bank is allocated to the heap region. The processor system may switch between first and second operating states. The first operating state has a lower power consumption than the second operating state. The processor system switches between a first and second operating mode by setting at least one memory bank and at least one further memory bank to an active state. The processor system switches between the second and first operating mode by setting at least one memory bank to a retention state and the at least one further memory bank to a power-down state.

## Claims

### Claim 1

A method of power management for a processor system including a processor coupled to a memory comprising a plurality of memory banks, the memory further comprising a region configurable as a heap region, wherein the processor is operable to execute instructions comprising one or more cryptographic operations; and wherein the method comprises:
allocating at least one memory bank to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation;
allocating at least one further memory bank to the heap region; and
switching from a first operating mode to a second operating mode by:
setting the at least one memory bank to an active state;
setting the at least one further memory bank to an active state; and
switching from the second operating mode to the first operating mode by:
setting the at least one memory bank to a retention state;
setting the at least one further memory bank to a power-down state.

### Claim 2 (depends on 1)

The method of claim 1 wherein the at least one memory bank is configured to store a public key.

### Claim 3 (depends on 2)

The method of claim 2 wherein the at least one cryptographic operation comprises a transport layer security (TLS) handshake operation.

### Claim 4 (depends on 1)

The method of claim 1 wherein the at least one cryptographic operation comprises at least one of an encryption operation and a decryption operation.

### Claim 5 (depends on 1)

The method of claim 1 wherein the at least one memory bank and the at least one further memory bank are non-contiguous.

### Claim 6 (depends on 1)

The method of claim 1 wherein allocating at least one memory bank to the heap region further comprises dividing the heap region into a plurality of sections, each section corresponding to a respective memory bank.

### Claim 7 (depends on 6)

The method of claim 6 further comprising providing an identifier for each cryptographic operation, providing the required heap size for each cryptographic operation and providing a section identifier comprising the address of a memory bank used as a starting point for each cryptographic operation.

### Claim 8 (depends on 7)

The method of claim 7 further comprising switching from the first operating mode to the second operating mode by:
setting a first memory bank to the active state;
checking whether the section identifier corresponds to the first memory bank;
in response to the section identifier corresponding to the first memory bank, determining whether the heap size exceeds the available memory in the first memory bank;
in response to the heap size exceeding the available memory in the first memory bank, setting a second memory bank to the active state;
in response to the section identifier not corresponding to the first memory bank, setting a third memory bank corresponding to the section identifier to the active state.

### Claim 9 (depends on 7)

The method of claim 7 further comprising:
checking whether the section identifier corresponds to the first memory bank;
allocating the first memory bank to the heap region;
in response to the section identifier corresponding to the first memory bank, determining whether the heap size exceeds the available memory in the first memory bank;
in response to the heap size exceeding the available memory in the first memory bank, allocating a second memory bank to the heap region;
in response to the section identifier not corresponding to the first memory bank, allocating a third memory bank corresponding to the section identifier to the heap region.

### Claim 10 (depends on 1)

The method of claim 1 further comprising determining the predetermined memory size required for execution of at least one cryptographic operation by:
determining the memory size to store the crypto-session elements for the at least one cryptographic operation;
determining the memory size to store the at least one cryptographic operation.

### Claim 11 (depends on 10)

The method of claim 10 wherein determining the predetermined memory size required for execution of at least one cryptographic operation further comprises running a static code analysis and a run-time code analysis.

### Claim 12

A processor system comprising a processor coupled to a memory comprising a plurality of memory banks, the memory further comprising a region configurable as a heap region, wherein the processor is operable to execute instructions comprising one or more cryptographic operations; and wherein the processor system is configured to:
allocate at least one memory bank to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation;
allocate at least one further memory bank to the heap region; and
further configured to switch from a first operating mode to a second operating mode by:
setting the at least one memory bank to an active state;
setting the at least one further memory bank to an active state; and
to switch from the second operating mode to the first operating mode by:
setting the at least one memory bank to a retention state;
setting the at least one further memory bank to a power-down state.

### Claim 13 (depends on 12)

The processor system of claim 12 further configured to provide an identifier for each cryptographic operation, provide the required heap size for each cryptographic operation and provide a section identifier comprising the address of a memory bank used as a starting point for each cryptographic operation.

### Claim 14 (depends on 13)

The processor system of claim 13 further configured to switch from the first operating mode to the second operating mode by:
setting a first memory bank to the active state;
checking whether the section identifier corresponds to the first memory bank;
in response to the section identifier corresponding to the first memory bank, determining whether the heap size exceeds the available memory in the first memory bank;
in response to the heap size exceeding the available memory in the first memory bank, setting a second memory bank to the active state;
in response to the section identifier not corresponding to the first memory bank, setting a third memory bank corresponding to the section identifier to the active state.

### Claim 15 (depends on 13)

The processor system of claim 13 further configured to:
check whether the section identifier corresponds to the first memory bank;
allocate the first memory bank to the heap region;
in response to the section identifier corresponding to the first memory bank, determining whether the heap size exceeds the available memory in the first memory bank;
in response to the heap size exceeding available memory in the first memory bank;
allocating a second memory bank to the heap region;
in response to the section identifier not corresponding to the first memory bank, allocating a third memory bank corresponding to the section identifier to the heap region.

### Claim 16

A non-transitory computer readable media comprising a computer program comprising computer executable instructions which, when executed by a processor system including a processor coupled to a memory comprising a plurality of memory banks, causes the processor to perform the steps of
allocating at least one memory bank to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation;
allocating at least one further memory bank to the heap region; and
switching from a first operating mode to a second operating mode by:
setting the at least one memory bank to an active state;
setting the at least one further memory bank to an active state; and
switching from the second operating mode to the first operating mode by:
setting the at least one memory bank to a retention state;
setting the at least one further memory bank to a power-down state.

### Claim 17 (depends on 16)

The non-transitory computer readable media of claim 16 further comprising computer executable instructions which causes the processor to perform the steps of allocating at least one memory bank to the heap region further comprises dividing the heap region into a plurality of sections, each section corresponding to a respective memory bank.

### Claim 18 (depends on 17)

The non-transitory computer readable media of claim 17 further comprising computer executable instructions which causes the processor to perform the steps of providing an identifier for each cryptographic operation, providing the required heap size for each cryptographic operation and providing a section identifier comprising the address of a memory bank used as a starting point for each cryptographic operation.

### Claim 19 (depends on 18)

The non-transitory computer readable media of claim 18 further comprising computer executable instructions which causes the processor to perform the steps of switching from the first operating mode to the second operating mode by:
setting a first memory bank to the active state;
checking whether the section identifier corresponds to the first memory bank;
in response to the section identifier corresponding to the first memory bank, determining whether the heap size exceeds the available memory in the first memory bank;
in response to the heap size exceeding the available memory in the first memory bank, setting a second memory bank to the active state;
in response to the section identifier not corresponding to the first memory bank, setting a third memory bank corresponding to the section identifier to the active state.

### Claim 20 (depends on 18)

The non-transitory computer readable media of claim 18 further comprising computer executable instructions which causes the processor to perform the steps of:
checking whether the section identifier corresponds to the first memory bank;
allocating the first memory bank to the heap region;
in response to the section identifier corresponding to the first memory bank, determining whether the heap size exceeds the available memory in the first memory bank;
in response to the heap size exceeding the available memory in the first memory bank, allocating a second memory bank to the heap region;
in response to the section identifier not corresponding to the first memory bank, allocating a third memory bank corresponding to the section identifier to the heap region.