# US 11,907,009 B2 · Phase detection circuit, clock generation circuit and semiconductor apparatus using the phase detection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,907,009 B2 - Document ID: US11907009B2 - Status: Granted - Kind: B2 - Application number: 17/975,010 - Filed: 2022-10-27 - Published: 2023-02-09 - Granted: 2024-02-20 - Earliest claimed: 2019-06-21 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Gyu Tae Park - Web page: https://patentgrep.com/patent/US11907009B2 ## CPC - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - H03K 5/24: the characteristic being amplitude - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal. ## Claims ### Claim 1 A phase detection circuit comprising: an edge trigger circuit configured to generate a falling clock signal by triggering edges of a reference clock signal and to generate a rising clock signal by triggering edges of the reference clock signal and a target clock signal; a strobe generation circuit configured to generate a falling strobe signal having a pulse width varying based on the falling clock signal and to generate a rising strobe signal having a pulse width varying based on the rising clock signal; and a phase detector configured to generate a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal. ### Claim 2 (depends on 1) The phase detection circuit according to claim 1, wherein the target clock signal has a phase lagging by 90 degrees with the reference clock signal, and wherein the edge trigger circuit generates: the falling clock signal having a pulse which enables during a period from a rising edge of the reference clock signal to a subsequent rising edge of the reference clock signal, and the rising clock signal having a pulse which enables during a period from a rising edge of the target clock signal to a rising edge of the reference clock signal. ### Claim 3 (depends on 2) The phase detection circuit according to claim 2, wherein the strobe generation circuit generates the falling strobe signal having a pulse which enables for a longer time than the rising strobe signal. ### Claim 4 (depends on 1) The phase detection circuit according to claim 1, wherein the target clock signal has a phase lagging by 180 degrees with the reference clock signal, and wherein the edge trigger circuit generates: the falling clock signal having a pulse, which enables during a period from a rising edge of the reference clock signal to a subsequent rising edge of the reference clock signal, and the rising clock signal having a pulse, which enables during a period from a rising edge of the reference clock signal to a rising edge of the target clock signal. ### Claim 5 (depends on 4) The phase detection circuit according to claim 4, wherein the strobe generation circuit generates the falling strobe signal having a pulse which enables for the same time with the rising strobe signal. ### Claim 6 (depends on 1) The phase detection circuit according to claim 1, wherein the target clock signal has a phase lagging by 270 degrees with the reference clock signal, and wherein the edge trigger circuit generates: the falling clock signal having a pulse, which enables during a period from a rising edge of the reference clock signal to a subsequent rising edge of the reference clock signal, and the rising clock signal having a pulse, which enables during a period from a rising edge of the reference clock signal to a rising edge of the target clock signal. ### Claim 7 (depends on 6) The phase detection circuit according to claim 6, wherein the strobe generation circuit generates the falling strobe signal having a pulse which enables for a longer time than the rising strobe signal. ### Claim 8 (depends on 1) The phase detection circuit according to claim 1, wherein the phase detection circuit detects pulses of the falling clock signal which occurs within the falling strobe signal and detects pulses of the rising clock signal which occurs within the rising strobe signal to generate the phase detection signal. ### Claim 9 (depends on 1) The phase detection circuit of claim 1, wherein the phase detector includes: a duty detector configured to generate a positive output signal based on the falling clock signal and the falling strobe signal and generate a negative output signal based on the rising clock signal and the rising strobe signal; and a comparator configured to generate the phase detection signal by comparing the positive output signal with the negative output signal. ### Claim 10 (depends on 9) The phase detection circuit of claim 9, wherein the duty detector includes: a first capacitor coupled to a positive output node; and a second capacitor coupled to a negative output node, wherein the duty detector outputs the positive output signal through the positive output node by discharging the positive output node based on the falling clock signal and the falling strobe signal; and outputs the negative output signal through the negative output node by discharging the negative output node based on the rising clock signal and the rising strobe signal, and wherein the first and second capacitors have substantially the same capacitance with each other. ### Claim 11 (depends on 1) The phase detection circuit of claim 1, wherein the strobe generation circuit varies the pulse width of the falling strobe signal based on a pulse width of the falling clock signal, and varies the pulse width of the rising strobe signal based on a pulse width of the falling clock signal. ### Claim 12 A phase detection circuit comprising: an edge trigger circuit configured to generate a falling clock signal having a pulse which enables during a period from a rising edge of a reference clock signal to a rising edge of a target clock signal and to generate a rising clock signal having a pulse which enables during a period from the rising edge of the target clock signal to a subsequent rising edge of the reference clock signal; a strobe generation circuit configured to generate a falling strobe signal having a pulse width varying based on the falling clock signal and to generate a rising strobe signal having a pulse width varying based on the rising clock signal; and a phase detector configured to generate a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal. ### Claim 13 (depends on 11) The phase detection circuit according to claim 11, wherein the strobe generation circuit generates, when the target clock signal has a phase lagging by 90 degrees with the reference clock signal, the falling strobe signal which enables for a longer time than the rising strobe signal. ### Claim 14 (depends on 11) The phase detection circuit according to claim 11, wherein the strobe generation circuit generates, when the target clock signal has a phase lagging by 180 degrees with the reference clock signal, the falling strobe signal and the rising strobe signal which enable for the same time with each other. ### Claim 15 (depends on 11) The phase detection circuit according to claim 11, wherein the strobe generation circuit generates, when the target clock signal has a phase lagging by 270 degrees with the reference clock signal, the rising strobe signal which enables for a longer time than the falling strobe signal. ### Claim 16 (depends on 11) The phase detection circuit according to claim 11, wherein the phase detection circuit detects pulses of the falling clock signal which occurs within the falling strobe signal and detects pulses of the rising clock signal which occurs within the rising strobe signal to generate the phase detection signal. ### Claim 17 (depends on 12) The phase detection circuit of claim 12, wherein the phase detector includes: a duty detector configured to generate a positive output signal based on the falling clock signal and the falling strobe signal and generate a negative output signal based on the rising clock signal and the rising strobe signal; and a comparator configured to generate the phase detection signal by comparing the positive output signal with the negative output signal. ### Claim 18 (depends on 17) The phase detection circuit of claim 17, wherein the duty detector includes: a first capacitor coupled to a positive output node; and a second capacitor coupled to a negative output node, wherein the duty detector outputs the positive output signal through the positive output node by discharging the positive output node based on the falling clock signal and the falling strobe signal; and outputs the negative output signal through the negative output node by discharging the negative output node based on the rising clock signal and the rising strobe signal, and wherein the first and second capacitors have substantially the same capacitance with each other. ### Claim 19 (depends on 12) The phase detection circuit of claim 12, wherein the strobe generation circuit varies the pulse width of the falling strobe signal based on a pulse width of the falling clock signal, and varies the pulse width of the rising strobe signal based on a pulse width of the falling clock signal.