# US 11,907,005 B2 · Clock management circuit and multi-core system including the same

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- Number: US 11,907,005 B2
- Document ID: US11907005B2
- Status: Granted
- Kind: B2
- Application number: 17/552,454
- Filed: 2021-12-16
- Published: 2022-10-27
- Granted: 2024-02-20
- Earliest claimed: 2021-04-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Geunho Choi; Mingoo Kang
- Web page: https://patentgrep.com/patent/US11907005B2

## CPC

- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 1/3237: by disabling clock generation or distribution
- G06F 1/324: by lowering clock frequency
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G06F 1/3243: {Power saving in microcontroller unit}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A multi-core system includes a multi-core processor, a function block, a clock management circuit, and a control circuit. The multi-core processor includes a plurality of processor cores configured to operate based on a plurality of core clock signals, respectively. The function block communicates with the multi-core processor based on an interface clock signal. The clock management circuit generates each of the plurality of core clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on each of a plurality of frequency selection signals. The clock management circuit generates the interface clock signal based on the second clock signal. A control circuit may generate the plurality of frequency selection signals corresponding to the plurality of processor cores, respectively.

## Claims

### Claim 1

A multi-core system comprising:
a multi-core processor including a plurality of processor cores configured to operate based on a plurality of core clock signals, respectively;
a function block configured to communicate with the multi-core processor based on an interface clock signal;
a clock management circuit configured to:
generate each of the plurality of core clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on each of a plurality of frequency selection signals,
generate the interface clock signal based on the second clock signal,
fix a frequency of the interface signal to the second frequency regardless of the plurality of frequency selection signals, and
change a frequency of each of the plurality of core deck signals between the frequency and the second frequency based on each of the plurality of frequency selection signals; and
a control circuit configured to generate the plurality of frequency selection signals corresponding to the plurality of processor cores, respectively.

### Claim 2 (depends on 1)

The multi-core system of claim 1, wherein the clock management circuit is further configured to:
generate a clock gating signal that is activated to control a clock gating period when a frequency of at least one of the plurality of core clock signals is changed, and
simultaneously deactivate the plurality of core clock signals and the interface clock signal in the clock gating period based on the clock gating signal.

### Claim 3 (depends on 1)

The multi-core system of claim 1, wherein the clock management circuit is further configured to generate a plurality of core strobe signals corresponding to the plurality of core clock signals based on the plurality of frequency selection signals, respectively,
wherein each of the plurality of processor cores is configured to communicate with the function block by the second frequency based on each of the plurality of core clock signals and each of the plurality of core strobe signals, and
wherein the function block is configured to communicate with the plurality of processor cores by the second frequency based on the interface clock signal.

### Claim 4 (depends on 1)

The multi-core system of claim 1, wherein the clock management circuit includes:
a synchronization circuit configured to generate a clock gating signal that is activated to control a clock gating period when a frequency of at least one of the plurality of core clock signals is changed;
a plurality of clock switching circuits configured to generate a plurality of switching clock signals by selecting one of the first clock signal and the second clock signal;
a plurality of core clock gating circuits configured to generate the plurality of core clock signals respectively corresponding to the plurality of switching clock signals by deactivating the plurality of switching clock signals during the clock gating period based on the clock gating signal; and
an interface clock gating circuit configured to generate the interface clock signal by deactivating the second clock signal during the clock gating period based on the clock gating signal.

### Claim 5 (depends on 4)

The multi-core system of claim 4, wherein each of the plurality of clock switching circuits includes:
a multiplexer configured to generate a switching clock signal of the plurality of switching clock signals by selecting one of the first clock signal and the second clock signal based on a clock switching signal that transitions at a clock changing time point.

### Claim 6 (depends on 4)

The multi-core system of claim 4, wherein each of the plurality of clock switching circuits includes:
a multiplexer configured to generate a selection clock signal by selecting one of the first clock signal and the second clock signal based on a clock switching signal that transitions at a clock changing time point; and
a glitch free circuit configured to generate a switching clock signal of the plurality of switching clock signals by removing a glitch at the clock changing time point from the selection clock signal.

### Claim 7 (depends on 4)

The multi-core system of claim 4, wherein the synchronization circuit includes:
an OR gate configured to generate a busy signal by performing an OR logic operation on a plurality of core busy signals where each of the plurality of core busy signal is activated when a frequency of each of the plurality of core clock signals is changed;
a first flip-flop circuit configured to generate a first enable signal by synchronizing the busy signal with the second clock signal;
a second flip-flop circuit configured to generate a second enable signal by synchronizing the first enable signal with the first clock signal; and
a multiplexer configured to generate the clock gating signal by selecting one of the first enable signal and the second enable signal based on the busy signal.

### Claim 8 (depends on 7)

The multi-core system of claim 7, wherein the synchronization circuit is configured to:
activate the clock gating signal based on transitioning of the first enable signal, and
deactivate the clock gating signal based on transitioning of the second enable signal.

### Claim 9 (depends on 4)

The multi-core system of claim 4, wherein each of the plurality of core clock gating circuits includes:
a latch circuit configured to generate a mask signal based on the clock gating signal and a switching clock signal of the plurality of switching clock signals; and
an AND gate configured to generate a core clock signal of the plurality of core clock signals by performing an AND operation on the mask signal and the switching clock signal.

### Claim 10 (depends on 4)

The multi-core system of claim 4, wherein the interface clock gating circuit includes:
a latch circuit configured to generate a mask signal based on the clock gating signal and the second clock signal; and
an AND gate configured to generate the interface clock signal by performing an AND operation on the mask signal and the second clock signal.

### Claim 11 (depends on 4)

The multi-core system of claim 4, wherein the clock management circuit further includes:
a plurality of core strobe generation circuits configured to generate a plurality of core strobe signals corresponding to the plurality of core clock signals based on a strobe signal having the second frequency and the plurality of frequency selection signals, respectively.

### Claim 12 (depends on 11)

The multi-core system of claim 11, wherein each of the plurality of core strobe generation circuits includes:
a strobe controller configured to generate a strobe switching signal based on a frequency selection signal of the plurality of frequency selection signals such that the strobe switching signal transitions in the clock gating period when a frequency of a core clock signal of the plurality of core clock signals is changed; and
an OR gate configured to generate a core strobe signal of the plurality of core strobe signals by performing an OR logic operation on the strobe switching signal and the strobe signal.

### Claim 13 (depends on 11)

The multi-core system of claim 11, wherein each of the plurality of core strobe generation circuits is configured to generate a core strobe signal of the plurality of core strobe signals:
toggling between a logic high level and a logic low level when a core clock signal of the plurality of core clock signals corresponds to the first clock signal, and
maintaining the logic high level when the core clock signal corresponds to the second clock signal.

### Claim 14 (depends on 11)

The multi-core system of claim 11, wherein each of the plurality of processor cores is configured to;
generate a core interface clock signal by performing an AND operation on a core clock signal of the plurality of core clock signals and a core strobe signal of the plurality of core strobe signals, and
communicate with the function block by the second frequency based on the core interface clock signal.

### Claim 15 (depends on 4)

The multi-core system of claim 4, wherein the clock management circuit further includes:
a clock divider configured to generate the second clock signal having the second frequency by dividing the first frequency of the first clock signal and configured to commonly provide the second clock signal to the plurality of clock switching circuits and the interface clock gating circuit.

### Claim 16

A multi-core system comprising:
a multi-core processor including a first processor core configured to operate based on a first core clock signal and a second processor core configured to operate based on a second core clock signal;
a function block configured to communicate with the multi-core processor based on an interface clock signal; and
a clock management circuit configured to:
generate the first core clock signal by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on a first frequency selection signal,
generate the second core clock signal by selecting one of the first clock signal and the second clock signal based on a second frequency selection signal,
generate the interface clock signal based on the second clock signal, and
when at least one of a frequency of the first core clock signal and a frequency of the second core clock signal is changed, simultaneously deactivate the first core clock signal, the second core clock signal and the interface clock signal in a clock gating period.

### Claim 17 (depends on 16)

The multi-core system of claim 16, wherein the clock management circuit is further configured to:
change a frequency of the first core clock signal between the first frequency and the second frequency based on the first frequency selection signal regardless of a frequency of the second core clock signal, and
change the frequency of the second core clock signal between the first frequency and the second frequency based on the second frequency selection signal regardless of the frequency of the first core clock signal.

### Claim 18 (depends on 16)

The multi-core system of claim 16, wherein the clock management circuit is configured to generate a first core strobe signal and a second core strobe signal corresponding to the first core clock signal and the second core clock signal based on the first frequency selection signal and the second frequency selection signal, respectively,
wherein the first processor core is configured to communicate with the function block by the second frequency based on the first core clock signal and the first core strobe signal,
wherein the second processor core is configured to communicate with the function block by the second frequency based on the second core clock signal and the second core strobe signal, and
wherein the function block is configured to communicate with the first processor core and the second processor core by the second frequency based on the interface clock signal.

### Claim 19

A clock management circuit comprising:
a synchronization circuit configured to generate a clock gating signal that is activated to control a clock gating period when a frequency of at least one of a plurality of core clock signals provided to a plurality of processor cores of a multi-core system is changed;
a plurality of clock switching circuits configured to a plurality of switching clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency;
a plurality of core clock gating circuits configured to generate the plurality of core clock signals respectively corresponding to the plurality of switching clock signals by deactivating the plurality of switching clock signals in the clock gating period based on the clock gating signal; and
an interface clock gating circuit configured to generate an interface clock signal provided to a function block of the multi-core system by deactivating the second clock signal in the clock gating period based on the clock gating signal.