# US 11,907,003 B2 · Output signal generation circuit

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- Number: US 11,907,003 B2
- Document ID: US11907003B2
- Status: Granted
- Kind: B2
- Application number: 18/156,148
- Filed: 2023-01-18
- Published: 2023-05-18
- Granted: 2024-02-20
- Earliest claimed: 2016-08-18
- Assignees: Lapis Semiconductor Co., Ltd.
- Applicants: LAPIS Semiconductor Co., Ltd.
- Inventors: Kenjiro Matoba; Kazuhiro Yamashita
- Web page: https://patentgrep.com/patent/US11907003B2

## CPC

- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- H03K 19/018521: {of complementary type, e.g. CMOS}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

## Claims

### Claim 1

An information generation device, comprising:
an information generation circuit configured to generate a first data signal including first information and a second data signal including second information; and
an output signal generation circuit including a first pulse generation circuit that receives the first data signal and generates a first pulse signal including the first information, a second pulse generation circuit that receives the second data signal and the first pulse signal and generates a second pulse signal in which the second information is superimposed on the first pulse signal, and an output circuit that outputs the second pulse signal.

### Claim 2 (depends on 1)

The information generation device according to claim 1, wherein
the first pulse signal has a first pulse width that is a minimum pulse width of the first pulse signal, and
the second pulse signal has a second pulse width smaller than the first pulse width.

### Claim 3 (depends on 1)

The information generation device according to claim 1, wherein the second pulse generation circuit includes:
a frequency division circuit configured to perform frequency division on a reference signal to generate a frequency division signal,
an AND circuit configured to output, as the second pulse signal, a logical conjunction of the first pulse signal and the frequency division signal,
an OR circuit configured to output a logical disjunction of the first pulse signal and the frequency division signal, and
a selector connected between output terminals of the AND circuit and the OR circuit, and the output circuit, the selector being configured to select an output of the AND circuit or an output of the OR circuit, and to output the selected output to the output circuit.

### Claim 4 (depends on 3)

The information generation device according to claim 3, wherein the second pulse generation circuit further includes a level switching circuit configured to supply to the selector a switching signal that determines whether to output the frequency division signal in the second pulse signal when the first pulse signal is at a first logic level, or when the first pulse signal is at a second logic level.

### Claim 5 (depends on 1)

A semiconductor system comprising:
the information generation device according to claim 1, and
a functional unit configured to be connected to the information generation device and receive the second pulse signal,
wherein the information generation circuit is configured to generate the first information and the second information to operate the functional unit.