# US 11,906,999 B2 · Voltage overshoot dampener in dropout condition > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,906,999 B2 - Document ID: US11906999B2 - Status: Granted - Kind: B2 - Application number: 17/708,350 - Filed: 2022-03-30 - Published: 2022-12-15 - Granted: 2024-02-20 - Earliest claimed: 2021-06-10 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Saurabh Rai; Venkateswarlu Ramaswamy Tiruvamattur; Ramakrishna Ankamreddi - Web page: https://patentgrep.com/patent/US11906999B2 ## CPC - G05F 1/575: characterised by the feedback circuit - G05F 1/565: sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract Described embodiments include a circuit for dampening overshoot in a voltage regulator. The circuit includes a first and second offset voltage circuits, each having an input coupled to an input voltage terminal. A first comparator has a first comparator input coupled to the first offset output, and a second comparator input coupled to a reference voltage terminal. A second comparator has a third comparator input coupled to an output of the second offset circuit, and a fourth comparator input coupled to a voltage regulator output. An OR gate has first and second logic inputs and a logic output. The first and second logic inputs are coupled to the outputs of the first and second comparators, respectively. A turn-off circuit has a turn-off input coupled to the logic output, and is configured to provide a turn-off signal at a turn-off output to stop current flow from the voltage regulator output. ## Claims ### Claim 1 A circuit for dampening overshoot in a voltage regulator, the circuit comprising: a first offset voltage circuit having a first offset input and a first offset output, the first offset input coupled to an input voltage terminal; a second offset voltage circuit having a second offset input and a second offset output, the second offset input coupled to the input voltage terminal; a first comparator having first and second comparator inputs and a first comparator output, the first comparator input coupled to the first offset output, and the second comparator input coupled to a reference voltage terminal; a second comparator having third and fourth comparator inputs and a second comparator output, the third comparator input coupled to the second offset output, and the fourth comparator input coupled to a voltage regulator output; an OR gate having first and second logic inputs and a logic output, the first logic input coupled to the first comparator output, and the second logic input coupled to the second comparator output; and a turn-off circuit having a turn-off input and a turn-off output, the turn-off input coupled to the logic output, and the turn-off circuit configured to provide a turn-off signal at the turn-off output to stop current flow from the voltage regulator output responsive to a logic high at the turn-off input. ### Claim 2 (depends on 1) The circuit of claim 1, further comprising a falling edge detection circuit having a falling edge circuit input and a falling edge circuit output, the falling edge circuit input coupled to the logic output, and the falling edge detection circuit configured to provide a falling edge signal at the falling edge circuit output in response to a falling edge of a signal at the falling edge circuit input. ### Claim 3 (depends on 2) The circuit of claim 2, further comprising a pulse generation circuit having a pulse circuit input and a pulse circuit output, the pulse circuit input coupled to the falling edge circuit output, and the pulse generation circuit configured to provide a pulse signal at the pulse circuit output in response to the falling edge signal. ### Claim 4 (depends on 3) The circuit of claim 3, further comprising: a reference discharge circuit having a reference discharge input and a reference discharge output, the reference discharge input coupled to the pulse circuit output, and the reference discharge circuit is configured to provide a discharge signal at the reference discharge output in response to the pulse signal; and a startup circuit having a startup input and a startup output, the startup input coupled to the pulse circuit output, and the startup circuit configured to provide a startup signal at the startup output in response to a pulse signal at the startup input. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the startup signal is configured to trigger a restart of the voltage regulator. ### Claim 6 (depends on 4) The circuit of claim 4, wherein a voltage at the second comparator input is brought to ground in response to the discharge signal. ### Claim 7 (depends on 2) The circuit of claim 2, wherein the falling edge circuit output is coupled to a control terminal of a transistor. ### Claim 8 (depends on 1) The circuit of claim 1, wherein a voltage at the first offset output is lower than a voltage at the second offset output. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the reference voltage terminal is coupled to a bandgap reference circuit. ### Claim 10 A voltage regulator circuit, comprising: a reference generation circuit having a reference input and a reference output, the reference input coupled to an input voltage terminal; a first amplifier having first and second amplifier inputs and a first amplifier output, the first amplifier input coupled to the reference output, and the second amplifier input coupled to an output voltage terminal; a second amplifier having a third amplifier input and a second amplifier output, the third amplifier input coupled to the first amplifier output; a first transistor coupled between the input voltage terminal and the first amplifier output, and having a first control terminal; a second transistor coupled between the input voltage terminal and the output voltage terminal, and having a second control terminal coupled to the second amplifier output; a first offset voltage circuit having a first offset input and a first offset output, the first offset input coupled to the input voltage terminal; a second offset voltage circuit having a second offset input and a second offset output, the second offset input coupled to the input voltage terminal; a first comparator having first and second comparator inputs and a first comparator output, the first comparator input coupled to the first offset output, and the second comparator input coupled to the reference output; a second comparator having third and fourth comparator inputs and a second comparator output, the third comparator input coupled to the second offset output, and the fourth comparator input coupled to the output voltage terminal; an OR gate having first and second logic inputs and a logic output, the first logic input coupled to the first comparator output, and the second logic input coupled to the second comparator output; and a turn-off circuit having a turn-off input and a turn-off output, the turn-off input coupled to the logic output, and the turn-off circuit configured to provide a turn-off signal at the first control terminal in response to a logic high at the turn-off input. ### Claim 11 (depends on 10) The voltage regulator circuit of claim 10, wherein the reference generation circuit includes a filter coupled between the reference output and a ground terminal. ### Claim 12 (depends on 10) The voltage regulator circuit of claim 10, further comprising a falling edge detection circuit having a falling edge circuit input and a falling edge circuit output, the falling edge circuit input coupled to the logic output, and the falling edge detection circuit configured to provide a falling edge signal at the falling edge circuit output in response to a falling edge of a signal at the falling edge circuit input. ### Claim 13 (depends on 12) The voltage regulator circuit of claim 12, further comprising a pulse generation circuit having a pulse circuit input and a pulse circuit output, the pulse circuit input coupled to the falling edge circuit output, and the pulse generation circuit configured to provide a pulse signal at the pulse circuit output in response to the falling edge signal. ### Claim 14 (depends on 13) The voltage regulator circuit of claim 13, further comprising: a reference discharge circuit having a reference discharge input and a reference discharge output, the reference discharge input coupled to the pulse circuit output, the reference discharge output coupled to the reference generation circuit, and the reference discharge circuit is configured to provide a discharge signal at the reference discharge output in response to the pulse signal; and a startup circuit having a startup input and a startup output, the startup input coupled to the pulse circuit output, and the startup circuit configured to provide a startup signal at the startup output in response to a pulse signal at the startup input. ### Claim 15 (depends on 14) The voltage regulator circuit of claim 14, wherein the startup signal is configured to trigger a restart of the voltage regulator circuit. ### Claim 16 (depends on 14) The voltage regulator circuit of claim 14, wherein a voltage at the reference output is brought to ground in response to the discharge signal. ### Claim 17 (depends on 10) The voltage regulator circuit of claim 10, wherein a voltage at the first offset output is lower than a voltage at the second offset output. ### Claim 18 (depends on 10) The voltage regulator circuit of claim 10, wherein the reference generation circuit includes a bandgap reference circuit. ### Claim 19 A method for dampening overshoot in a voltage regulator, the method comprising: supplying an input voltage to a voltage regulator input and enabling a voltage regulator output; generating a reference voltage at a reference voltage output; regulating an output voltage at the voltage regulator output by comparing the reference voltage to a feedback voltage proportional to the output voltage; comparing a first offset voltage to a difference between the input voltage and the output voltage, and comparing a second offset voltage to a difference between the input voltage and the reference voltage; and disabling the voltage regulator output responsive to either the first offset voltage being greater than the difference between the input voltage and the output voltage, or the second offset voltage being greater than the difference between the input voltage and the reference voltage. ### Claim 20 (depends on 19) The method of claim 19, further comprising: discharging the output voltage and the reference voltage in response to the first offset voltage no longer being greater than the difference between the input voltage and the output voltage, and the second offset voltage no longer being greater than the difference between the input voltage and the reference voltage.