# US 11,906,997 B2 · Low-dropout (LDO) voltage regulator including amplifier and decoupling capacitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,906,997 B2 - Document ID: US11906997B2 - Status: Granted - Kind: B2 - Application number: 17/456,934 - Filed: 2021-11-30 - Published: 2022-11-17 - Granted: 2024-02-20 - Earliest claimed: 2021-05-14 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Szu-Chun Tsao; Yi-Wen Chen; Jaw-Juinn Horng - Web page: https://patentgrep.com/patent/US11906997B2 ## CPC - G05F 1/575: characterised by the feedback circuit - G05F 1/565: sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) - H03K 19/018521: {of complementary type, e.g. CMOS} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A middle-range (mid) low dropout (LDO) voltage has both sinking and sourcing current capability. The mid LDO can provide a voltage reference in active mode and power mode for core only design to work in a Safe Operating Area (SOA). The output of mid LDO can track TO power and/or core power dynamically. The mid LDO can comprise a voltage reference generator and a power-down controller connected to an amplifier, which output is connected to a decoupling capacitor. The provision of a high ground signal allows the mid LDO provide the sinking and sourcing currents. ## Claims ### Claim 1 A Low-Dropout voltage regulator (LDO) comprising: an amplifier supplied with a voltage reference (VREF) input, the amplifier configured to produce a source current to or a sinking current from a load; and a decoupling capacitor, connected to an output of the amplifier, configured to decouple a high-edge ground (HGND) from a power source, the decoupling capacitor including a first capacitor and a second capacitor attached with the load, wherein the first capacitor is a pure Metal-Oxide-Metal (MOM) capacitor (CMOM) and the second capacitor is a core P-type Metal Oxide Semiconductor Capacitor (PMOSCAP), wherein one or more Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) is placed beneath the CMOM to get a highest capacitance density. ### Claim 2 (depends on 1) The LDO of claim 1, further comprising: a Power Down Control Unit (PDCTRL) configured to maintain the HGND in an active mode or a power-down mode. ### Claim 3 (depends on 2) The LDO of claim 2, wherein the PDCTRL comprises a resistor and a diode-connected MOSFET, wherein the diode-connected MOSFET is either PMOS or NMOS, and wherein the resistor is placed between the diode-connected MOSFET and a core power for biasing. ### Claim 4 (depends on 2) The LDO of claim 2, wherein the amplifier comprises a push PMOS to the load and a pull NMOS from the load. ### Claim 5 (depends on 4) The LDO of claim 4, wherein the push PMOS and the pull NMOS share a drain to connect with the load. ### Claim 6 (depends on 5) The LDO of claim 5, wherein a gate bias of the push PMOS and the pull NMOS is controlled by either a single amplifier or a dual amplifier. ### Claim 7 (depends on 6) The LDO of claim 6, wherein the amplifier is a Class-AB folded cascode type amplifier. ### Claim 8 (depends on 1) The LDO of claim 1, wherein a first output of the first capacitor is connected to ground. ### Claim 9 (depends on 8) The LDO of claim 8, wherein a second output of the second capacitor is connected to the core power or an IO power. ### Claim 10 (depends on 1) The LDO of claim 1, further comprising: a Voltage Reference Generator (VREFGEN) circuit, connected to an input of the amplifier, the VREFGEN configured to track a fixed voltage reference and supply the VREF input to the amplifier. ### Claim 11 A level shifter comprising: a Low-Dropout voltage regulator (LDO) comprising: an amplifier configured to produce a source current to or a sinking current from a load; a Voltage Reference Generator (VREFGEN) circuit, connected to an input of the amplifier, configured to track a fixed voltage reference (VREF) and supply a voltage reference output (VREFM) to the amplifier; a decoupling capacitor, connected to an output of the amplifier, configured to decouple a high-edge ground (HGND) from a power source; and a Power Down Control Unit (PDCTRL) configured to maintain the HGND in an active mode or a power-down mode; wherein the VREFM of the LDO is directly forced by an input voltage or is forced through the VREFGEN, which is configured to transfer directly a difference between a core power and an IO power. ### Claim 12 (depends on 11) The level shifter of claim 11, wherein the VREFGEN is configured to transform directly core power information into a current through a core diode connected MOSFET and a resistor in series. ### Claim 13 (depends on 11) The level shifter of claim 11, wherein a sensing current VREFGEN is configured to generate the VREFM for the LDO through a second diode connected MOSFET and a second resistor between the IO power and the voltage reference to the LDO. ### Claim 14 A method comprising: receiving a voltage reference input at a Low-Dropout voltage regulator (LDO); receiving an Input/Output (IO) power at the LDO; receiving a high-edge ground (HGND) from a power source; and providing an output voltage from the LDO to a core design, wherein the output voltage is a difference between the IO power and the HGND, wherein providing the output voltage comprises: in a first configuration, producing a source current to the core design; or in a second configuration, receiving a sinking current from the core design, tracking a second difference between the IO power and a core power to supply the voltage reference input to the LDO, wherein tracking the second difference comprises: transforming core power information into a current through a core diode-connected Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) and a resistor in series; and generating the voltage reference input for the LIDO through a second diode-connected MOSFET and a second resistor between the IO power and the reference voltage input to the LDO. ### Claim 15 (depends on 14) The method of claim 14, further comprising: decoupling the HGND from the IO power; and maintaining the HGND in an active mode or a power-down mode. ### Claim 16 (depends on 10) The LDO of claim 10, wherein the VREFGEN circuit is configured to transform directly core power information into a current through a core diode connected MOSFET and a resistor in series. ### Claim 17 (depends on 11) The level shifter of claim 11, wherein the PDCTRL comprises a resistor and a diode-connected MOSFET. ### Claim 18 (depends on 17) The level shifter of claim 17, wherein the diode-connected MOSFET is either PMOS or NMOS, and wherein the resistor is placed between the diode-connected MOSFET and a core power for biasing. ### Claim 19 (depends on 11) The level shifter of claim 11, wherein the decoupling capacitor comprises a first capacitor and a second capacitor attached with the load, wherein the first capacitor is a pure Metal-Oxide-Metal (MOM) capacitor (CMOM) and the second capacitor is a core P-type Metal Oxide Semiconductor Capacitor (PMOSCAP). ### Claim 20 (depends on 19) The level shifter of claim 19, wherein one or more Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is placed beneath the CMOM to get a highest capacitance density.