# US 11,906,577 B2 · Pad structure and testkey structure and testing method for semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,906,577 B2 - Document ID: US11906577B2 - Status: Granted - Kind: B2 - Application number: 17/555,963 - Filed: 2021-12-20 - Published: 2022-12-22 - Granted: 2024-02-20 - Earliest claimed: 2021-06-21 - Assignees: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Applicants: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. - Inventors: Linzhi Lu; Le Li; Jiwei He - Web page: https://patentgrep.com/patent/US11906577B2 ## CPC - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - G01R 31/2887: {involving moving the probe head or the IC under test; docking stations (moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392)} - G01R 31/2889: {Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence)} - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure provides a pad structure and a testkey structure and a testing method for a semiconductor device. The pad structure includes: an insulating dielectric layer formed on a substrate; a metal interconnection structure formed in the insulating dielectric layer, the metal interconnection structure comprising a first section and a second section, which are insulated from each other; and a pad formed on the top of the insulating dielectric layer so as to be exposed therefrom at least at its top surface, electrically connected to the first section, and insulated from the second section. With this disclosure, reduced capture of plasma is achievable, mitigating adverse impact of plasma on the semiconductor device. ## Claims ### Claim 1 A pad structure, comprising: an insulating dielectric layer formed on a substrate; a metal interconnection structure formed in the insulating dielectric layer, the metal interconnection structure comprising a first section and a second section, which are insulated from each other; and a pad that is formed on a top of the insulating dielectric layer so that at least a top surface of the pad is exposed from the insulating dielectric layer, wherein the pad is electrically connected to the first section, and insulated from the second section. ### Claim 2 (depends on 1) The pad structure of claim 1, wherein each of the first section and the second section comprises a plurality of metal layers and a plurality of conductive plugs, the metal layers formed in the insulating dielectric layer vertically one above another so that adjacent ones of metal layers are electrically connected to each other by the conductive plugs. ### Claim 3 (depends on 1) The pad structure of claim 1, wherein the first section surrounds the second section. ### Claim 4 (depends on 1) The pad structure of claim 1, wherein the second section surrounds the first section. ### Claim 5 (depends on 1) The pad structure of claim 1, wherein the first section is an annular or elongate structure. ### Claim 6 (depends on 2) The pad structure of claim 2, wherein the metal layers in the first section have a cross-sectional area that is smaller than a cross-sectional area of the metal layers in the second section. ### Claim 7 (depends on 1) The pad structure of claim 1, wherein the substrate comprises a lower substrate, an intermediate buried insulating layer disposed over the lower substrate, and an upper semiconductor layer disposed over the intermediate buried insulating layer. ### Claim 8 (depends on 7) The pad structure of claim 7, wherein an STI structure is formed in the semiconductor layer. ### Claim 9 (depends on 8) The pad structure of claim 8, wherein the STI structure has a bottom side in contact with the buried insulating layer, wherein a vertical projection of the first section in the semiconductor layer overlaps at least part of the STI structure. ### Claim 10 (depends on 8) The pad structure of claim 8, wherein the pad structure further comprises a hole plug having one end electrically connected to the first section, and a further end extends from the insulating dielectric layer through the STI structure and the buried insulating layer so as to come into contact with the lower substrate. ### Claim 11 (depends on 10) The pad structure of claim 10, wherein the one end of the hole plug is electrically connected to a bottom of the first section. ### Claim 12 (depends on 1) The pad structure of claim 1, wherein a distance is formed between the first section and the second section. ### Claim 13 (depends on 1) The pad structure of claim 1, wherein a constant distance is formed between the first section and the second section. ### Claim 14 (depends on 1) The pad structure of claim 1, wherein the metal interconnection structure is insulated from the substrate. ### Claim 15 (depends on 1) The pad structure of claim 1, wherein each of the first section and the second section comprises four metal layers and a plurality of conductive plugs, the metal layers formed in the insulating dielectric layer vertically one above another so that adjacent ones of metal layers are electrically connected to each other by the conductive plugs. ### Claim 16 A testkey structure for a semiconductor device, the testkey structure comprising: a substrate; at least two pad structures formed on the substrate, each of the pad structure comprising: an insulating dielectric layer formed on the substrate; a metal interconnection structure formed in the insulating dielectric layer, the metal interconnection structure comprising a first section and a second section, which are insulated from each other; and a pad that is formed on a top of the insulating dielectric layer so that at least a top surface of the pad is exposed from the insulating dielectric layer, wherein the pad is electrically connected to the first section, and insulated from the second section; and a test pattern formed in an insulating dielectric layer of the substrate, wherein the first sections of the pad structures are electrically connected to, and the second sections of the pad structures are insulated from, the test pattern. ### Claim 17 (depends on 16) The testkey structure of claim 16, wherein each of the first section and the second section comprises a plurality of metal layers and a plurality of conductive plugs, the metal layers formed in the insulating dielectric layer vertically one above another so that adjacent ones of metal layers are electrically connected to each other by the conductive plugs. ### Claim 18 (depends on 16) The testkey structure of claim 16, wherein the first section surrounds the second section. ### Claim 19 (depends on 17) The testkey structure of claim 17, wherein the metal layers in the first section have a cross-sectional area that is smaller than a cross-sectional area of the metal layers in the second section. ### Claim 20 (depends on 16) A testing method for a semiconductor device, the testing method comprising: providing a testkey structure as defined in claim 16; and bringing probe needles on a tester into contact with the top surfaces of the pads that are exposed from the insulating dielectric layers in the testkey structure and applying voltages or currents to the test pattern.