Reducing junction resistance variation in two-step deposition processes
AssigneeGoogle Inc.
InventorBrian James Burkett
Life of this patent
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AssigneeGoogle Inc.
InventorBrian James Burkett
Estimating the term…
A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate, forming a first resist layer on the dielectric substrate, forming a second resist layer on the first resist layer, and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through a thickness of the third resist layer.
A method comprising:
A method comprising:
Dependencies are inferred from the claim text.