# US 11,903,325 B2 · Magnetic memory device having shared source line and bit line

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- Number: US 11,903,325 B2
- Document ID: US11903325B2
- Status: Granted
- Kind: B2
- Application number: 17/735,094
- Filed: 2022-05-02
- Published: 2022-08-18
- Granted: 2024-02-13
- Earliest claimed: 2020-04-01
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Yi-Ting Wu; Yan-Jou Chen; Cheng-Tung Huang; Jen-Yu Wang; Po-Chun Yang; Yung-Ching Hsieh; Jian-Jhong Chen; Bo-Chang Li
- Web page: https://patentgrep.com/patent/US11903325B2

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- H10N 50/80: Constructional details
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 11/15: using multiple magnetic layers (G11C11/155 takes precedence)
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1659: {Cell access}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/85: Materials of the active region
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.

## Claims

### Claim 1

A memory device, comprising:
a substrate;
a plurality of active areas extending along a first direction on the substrate;
a gate line traversing the active areas and extending along a second direction that is not parallel to the first direction;
a plurality of source doped regions in the active areas and on a first side of the gate line, wherein the plurality of source doped regions are substantially aligned along the second direction;
a main source line extending along the first direction;
a source line extension coupled to the main source line and extending along the second direction, wherein the source line extension elongates from opposite side edges of the main source line and electrically connects the plurality of source doped regions with the main source line;
a plurality of drain doped regions in the active areas and on a second side of the gate line that is opposite to the first side; and
a plurality of data storage elements electrically coupled to the drain doped regions, respectively.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein each of the plurality of data storage elements comprises a magnetic tunneling junction (MTJ) element.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein the MTJ element comprises a bottom electrode.

### Claim 4 (depends on 3)

The memory device according to claim 3 further comprising:
a landing pad disposed directly under the MTJ element.

### Claim 5 (depends on 4)

The memory device according to claim 4 further comprising:
a drain contact electrically connecting the landing pad to each of the plurality of drain doped regions.

### Claim 6 (depends on 5)

The memory device according to claim 5, wherein the bottom electrode is electrically connected to the landing pad.

### Claim 7 (depends on 3)

The memory device according to claim 3, wherein the MTJ element comprises a top electrode.

### Claim 8 (depends on 7)

The memory device according to claim 7, wherein the top electrode is electrically connected to a bit line.

### Claim 9 (depends on 8)

The memory device according to claim 8, wherein the bit line extends along the first direction.

### Claim 10 (depends on 4)

The memory device according to claim 4 further comprising:
a first dielectric layer disposed on the substrate, wherein the landing pad is disposed in the first dielectric layer and is situated in a first horizontal plane; and
a second dielectric layer covering the first dielectric layer and the landing pad, wherein the MTJ element is disposed in the second dielectric layer, and wherein the main source line and the source line extension are situated in a second horizontal plane.

### Claim 11 (depends on 10)

The memory device according to claim 10, wherein the second horizontal plane is lower than the first horizontal plane.