Display panel and display apparatus
AssigneeXiamen Tianma Micro-Electronics Co., Ltd.
InventorsJieliang Li, Jiaxian Liu
Life of this patent
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Abstract
Provided are a display panel and a display apparatus. The display panel includes a driving array layer having functional layers and insulation layers. The driving array layer includes a first transistor, a second transistor, a first capacitor including a first plate and a second plate, and a second capacitor including a third plate and a fourth plate. An active layer of the first transistor contains silicon, and an active layer of the second transistor contains oxide semiconductor. The first plate and the second plate are located in two of the functional layers, respectively, and the third plate and the fourth plate are located in two of the functional layers, respectively.
Claims17
A display panel, comprising:
- a base substrate;
- and
- a driving array layer disposed on the base substrate and having functional layers and insulation layers,
- wherein the driving array layer comprises:
- a first transistor, wherein the first transistor comprises a first active layer comprising silicon;
- a second transistor, wherein the second transistor comprises a second active layer comprising oxide semiconductor;
- a first capacitor comprising a first plate and a second plate;
- and
- a second capacitor comprising a third plate and a fourth plate,
- wherein a first insulation layer is provided between the first plate and the second plate, and a second insulation layer is provided between the third plate and the fourth plate;
- the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode and the first active layer, wherein the first gate electrode is located at a side of the first active layer away from the base substrate;
- the second transistor comprises a second gate electrode, a third gate electrode, a second source electrode, a second drain electrode and the second active layer, wherein the second gate electrode is located between the second active layer and the base substrate;
- and the third gate electrode is located at a side of the second active layer away from the base substrate;
- and
- the first gate electrode is located in a first metal layer, the second gate electrode is located in a second metal layer, and the third gate electrode is located in a third metal layer.
A display panel, comprising:
- a base substrate;
- and
- a driving array layer disposed on the base substrate and having functional layers and insulation layers,
- wherein the driving array layer comprises:
- a first transistor, wherein the first transistor comprises a first active layer comprising silicon;
- a second transistor, wherein the second transistor comprises a second active layer comprising oxide semiconductor;
- a first capacitor comprising a first plate and a second plate;
- and
- a second capacitor comprising a third plate and a fourth plate,
- wherein a first insulation layer is provided between the first plate and the second plate, and a second insulation layer is provided between the third plate and the fourth plate;
- wherein the driving array layer comprises:
- a pixel circuit comprising the second capacitor;
- and
- a driving circuit configured to provide a control signal to the pixel circuit and comprising the first capacitor,
- wherein the first capacitor has a greater capacitance than the second capacitor;
- and
- wherein the pixel circuit comprises the first capacitor, and the driving circuit comprises the second capacitor;
- and an orthographic projection of the second capacitor on a plane of the display panel partially overlaps an orthographic projection of the first transistor on the plane of the display panel, and an orthographic projection of the first capacitor on the plane of the display panel partially does not overlap an orthographic projection of the second transistor on the plane of the display panel;
- or
- the pixel circuit comprises the first transistor, and the driving circuit comprises the second transistor, and an area of a region where an orthographic projection of the second capacitor on a plane of the display panel overlaps an orthographic projection of the first transistor of the pixel circuit on the plane of the display panel is greater than an area of a region where an orthographic projection of the first capacitor on the plane of the display panel overlaps an orthographic projection of the second transistor on the plane of the display panel.
A display apparatus, comprising:
- a display panel, comprising a base substrate and a driving array layer, the driving array layer being disposed on the base substrate and having functional layers and insulation layers,
- wherein the driving array layer comprises:
- a first transistor, wherein the first transistor comprises a first active layer comprising silicon;
- a second transistor, wherein the second transistor comprises a second active layer comprising oxide semiconductor;
- a first capacitor comprising a first plate and a second plate;
- and
- a second capacitor comprising a third plate and a fourth plate,
- wherein a first insulation layer is provided between the first plate and the second plate, and a second insulation layer is provided between the third plate and the fourth plate;
- and the first insulation layer has a greater hydrogen content than the second insulation layer;
- the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode and the first active layer, wherein the first gate electrode is located at a side of the first active layer away from the base substrate;
- the second transistor comprises a second gate electrode, a third gate electrode, a second source electrode, a second drain electrode and the second active layer, wherein the second gate electrode is located between the second active layer and the base substrate;
- and the third gate electrode is located at a side of the second active layer away from the base substrate;
- and
- the first gate electrode is located in a first metal layer, the second gate electrode is located in a second metal layer, and the third gate electrode is located in a third metal layer.
Dependencies are inferred from the claim text.