Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors

An apparatus comprising:

• a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
• a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias;
• a stack of vertical vias which is coupled to the storage node;
• a plurality of metal layers coupled to the stack of vertical vias;
• and
• a plurality of capacitors having a first terminal coupled to the plurality of metal layers, wherein the plurality of capacitors includes capacitors on either side of the stack of vertical vias, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are planar capacitors.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a memory circuitry to store the one or more instructions;
• and
• a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, and wherein an individual bit-cell of the plurality of bit-cells includes:
• a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
• a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias;
• and
• a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are planar capacitors that are arranged in a stacked and folded configuration.