US 11,903,207 B2 · Method for writing data of a first memory cell transistor of a nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Claims20

Dependent claims

A method for writing data of a first memory cell transistor of a nonvolatile semiconductor memory device comprising:

applying a first voltage to a gate of a first select transistor, the first select transistor being coupled between a first bit line and a first memory unit having the first memory cell transistor and a second memory cell transistor coupled in series, the first memory cell transistor and the second memory cell transistor being arranged in a first direction crossing a surface of a substrate;
applying a second voltage lower than the first voltage to a gate of a second select transistor, the second select transistor being coupled between the first bit line and a second memory unit having a third memory cell transistor and a fourth memory cell transistor coupled in series, the third memory cell transistor and the fourth memory cell transistor being arranged in the first direction, a gate of the first memory cell transistor being coupled with a gate of the third memory cell transistor, the gate of the second memory cell transistor being coupled with a gate of the fourth memory cell transistor, the gate of the first select transistor not being coupled with a gate of the second select transistor;
and
applying a program voltage to the gate of the first memory cell transistor for writing data of the first memory cell transistor and applying a pass voltage to the gate of the second memory cell transistor, the pass voltage being lower than the program voltage.

1 more element

A method for writing data of a first memory cell transistor of a nonvolatile semiconductor memory device comprising:

turning on a first select transistor, the first select transistor being coupled between a first bit line and a first memory unit having the first memory cell transistor and a second memory cell transistor coupled in series, the first memory cell transistor and the second memory cell transistor being arranged in a first direction crossing a surface of a substrate;
turning off a second select transistor, the second select transistor being coupled between the first bit line and a second memory unit having a third memory cell transistor and a fourth memory cell transistor coupled in series, the third memory cell transistor and the fourth memory cell transistor being arranged in the first direction, a gate of the first memory cell transistor being coupled with a gate of the third memory cell transistor, a gate of the second memory cell transistor being coupled with a gate of the fourth memory cell transistor, a gate of the first select transistor not being coupled with a gate of the second select transistor;
and
applying a program voltage to the gate of the first memory cell transistor for writing data of the first memory cell transistor and applying a pass voltage to the gate of the second memory cell transistor, the pass voltage being lower than the program voltage.

1 more element

A method for writing data of a first memory cell transistor of a nonvolatile semiconductor memory device, comprising:

applying a first voltage to a gate of a first select transistor of the nonvolatile semiconductor memory device;
and
applying a second voltage lower than the first voltage to a gate of a second select transistor of the nonvolatile semiconductor memory device,
wherein the nonvolatile semiconductor memory device has a substrate, a first bit line, a first memory string and a second memory string, the first memory string being coupled with the first bit line, the first memory string extending in a first direction crossing a surface of the substrate, the first memory string having the first select transistor, the first memory cell transistor and a second memory cell transistor coupled in series, the first select transistor being between the first bit line and the first memory cell transistor, the second memory string being coupled with the first bit line, the second memory string having the second select transistor, a third memory cell transistor and a fourth memory cell transistor coupled in series, the second select transistor being between the first bit line and the third memory cell transistor, a gate of the first memory cell transistor being coupled with a gate of the third memory cell transistor, a gate of the second memory cell transistor being coupled with a gate of the fourth memory cell transistor, the gate of the first select transistor not being coupled with the gate of the second select transistor, and
wherein the method for writing data of a first memory cell transistor of a nonvolatile semiconductor memory device includes applying a program voltage to the gate of the first memory cell transistor for writing data of the first memory cell transistor and applying a pass voltage to the gate of the second memory cell transistor, the pass voltage being lower than the program voltage.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/750,207Filed 20 May 2022 · continuation

Priority

JP 2006-08667427 Mar 2006

Published

US 2022/0328517 A113 Oct 2022

Granted

13 Feb 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/20
EEPROM devices comprising charge-trapping gate insulators: characterised by three-dimensional [3D] arrangements, e.g. with cells on different…
H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region

Family

Application11/654,551Parent of this division · filed 18 Jan 2007

Application13/064,559Parent of this continuation · filed 31 Mar 2011

US 7,936,004 B2Parent of this division · filed 3 May 2011

Application13/198,359Parent of this continuation · filed 4 Aug 2011

US 8,551,838 B2Parent of this continuation · filed 8 Oct 2013

Application14/724,853Parent of this continuation · filed 29 May 2015

US 9,064,735 B2Parent of this continuation · filed 23 Jun 2015

Application15/666,653Parent of this continuation · filed 2 Aug 2017

US 9,748,260 B2Parent of this continuation · filed 29 Aug 2017

Application16/245,271Parent of this continuation · filed 11 Jan 2019

US 10,211,219 B2Parent of this continuation · filed 19 Feb 2019

Application17/141,534Parent of this continuation · filed 5 Jan 2021

US 10,916,559 B2Parent of this continuation · filed 9 Feb 2021

US 2022/0328517 A1Pre-grant publication · published 13 Oct 2022

US 11,374,021 B2Parent of this continuation

Application13/064,559Parent of this division

US 2007/0252201 A1Published application

US 2011/0284947 A1Published application

US 2011/0287597 A1Published application

US 2015/0372006 A1Published application

US 2017/0338244 A1Published application

US 2019/0148404 A1Published application

US 2021/0126012 A1Published application

US 11,903,207 B2This patent

From the US filing history. Foreign family members aren’t listed.

Method for writing data of a first memory cell transistor of a nonvolatile semiconductor memory device

Life of this patent

Method for writing data of a first memory cell transistor of a nonvolatile semiconductor memory device

Life of this patent

Abstract

Claims20