Three-dimensional semiconductor device

A three-dimensional semiconductor device, comprising:

• a peripheral circuit region;
• a stack structure on the peripheral circuit region, the stack structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a vertical direction, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape;
• a first insulating region and a second insulating region in the extension region, the first insulating region and the second insulating region penetrating through the stack structure, and being spaced apart from each other in a first direction;
• and
• a vertical channel structure penetrating through the stack structure within the memory cell array region;
• peripheral contact plugs penetrating through the first insulating region and the second insulating region;
• and
• a separation structure penetrating through the stack structure,
• wherein, in a plan view, the stack structure surrounds an entire side surface of the first insulating region,
• wherein the separation structure includes a first line portion and a second line portion,
• wherein the separation structure further includes a third line portion, a fourth line portion, a fifth line portion, and a sixth line portion between the first line portion and the second line portion, and
• wherein the fifth line portion and the sixth line portion are between the first insulating region and the second insulating region, the fifth line portion and the sixth line portion being spaced apart from each other in the first direction.

A three-dimensional semiconductor device, comprising:

• an upper substrate;
• a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape;
• and
• at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region, and an entire perimeter of each of the lower region and the upper region of the at least one through region being surrounded by the gate-stacked structure, as viewed in a top view.