US 11,903,202 B2 · Method of manufacturing semiconductor device

Abstract

In one embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer including a plurality of metal atoms on a substrate, and forming a first layer including a plurality of silicon atoms and a plurality of nitrogen atoms on the semiconductor layer. The method further includes transferring at least some of the metal atoms in the semiconductor layer into the first layer. and removing the first layer after transferring the at least some of the metal atoms in the semiconductor layer into the first layer. Furthermore, a ratio of a number of the nitrogen atoms relative to a number of the silicon atoms and the nitrogen atoms in the first layer is smaller than 4/7.

Claims20

Dependent claims

A method of manufacturing a semiconductor device, comprising:

forming a semiconductor layer including a plurality of metal atoms on a substrate;
forming a first layer including a plurality of silicon atoms and a plurality of nitrogen atoms on the semiconductor layer;
transferring at least some of the metal atoms in the semiconductor layer into the first layer;
and
removing the first layer after transferring the at least some of the metal atoms in the semiconductor layer into the first layer,
wherein a ratio of a number of the nitrogen atoms relative to a number of the silicon atoms and the nitrogen atoms in the first layer is smaller than 4/7.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/393,642Filed 4 Aug 2021

Priority

JP 2021-04620319 Mar 2021

Published

US 2022/0302158 A122 Sep 2022

Granted

13 Feb 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10D 64/037
Of data-storage electrodes: comprising charge-trapping insulators
H10D 30/693
IGFETs having charge trapping gate insulators, e.g. MNOS transistors: vertical IGFETs having charge trapping gate insulators
H10P 32/1408
Within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase: from or…

Method of manufacturing semiconductor device

Life of this patent

Method of manufacturing semiconductor device

Life of this patent

Abstract

Claims20