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US 11,903,199 B2Granted
Through via structure, semiconductor device including the through via structure, and massive data storage system including the semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsJeeyong Kim, Junghwan Lee
Life of this patent
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Abstract
A through via structure includes a through via and a capping pattern. The through via includes a metal pattern extending in a vertical direction, and a barrier pattern on a sidewall and a lower surface of the metal pattern. The capping pattern contacts an upper surface of the through via. A lowermost surface of an edge portion of the capping pattern is not higher than a lowermost surface of a central portion of the capping pattern.
Claims19
A through via structure comprising:
- a through via including
- a metal pattern, the metal pattern extending in a vertical direction and fully enclosing a gap in the metal pattern, wherein the metal pattern includes a seam extending vertically from the gap in the metal pattern, and wherein an etching gas used to form the metal pattern remains in the gap in the metal pattern,
- and
- a barrier pattern on a sidewall and a lower surface of the metal pattern;
- and
- a capping pattern contacting an upper surface of the through via, the capping pattern including a lowermost edge portion, and the lowermost edge portion of the capping pattern is not higher than a lowermost central portion of the capping pattern.
3 more elements
A through via structure comprising:
- an insulating interlayer;
- a through via including a metal pattern extending through the insulating interlayer in a vertical direction, the metal pattern including a first metal and a gap fully enclosed in the metal pattern, wherein the metal pattern includes a seam extending vertically from the gap in the metal pattern, and wherein an etching gas used to form the metal pattern remains in the gap in the metal pattern,
- and
- a barrier pattern on a sidewall and a lower surface of the metal pattern, the barrier pattern including a nitride of a second metal;
- and
- a first capping pattern contacting an upper surface of the through via, the first capping pattern including at least one of a silicide of the first metal or a compound of the first metal and silicon nitride, the first capping pattern-including a lowermost edge portion, the lower most edge portion of the first capping pattern is not higher than a lowermost central portion of the first capping pattern.
3 more elements
A semiconductor device comprising:
- lower circuit patterns on a substrate;
- a common source plate (CSP) over the lower circuit patterns;
- a gate electrode structure on the CSP, the gate electrode structure including gate electrodes spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate;
- a memory channel structure extending through the gate electrode structure on the substrate and connected to the CSP, the memory channel structure including
- a channel extending in the vertical direction, and
- a charge storage structure surrounding an outer sidewall of the channel;
- and
- a through via structure including a through via having
- a metal pattern extending in the vertical direction and fully enclosing a gap in the metal pattern, wherein the metal pattern includes a seam extending vertically from the gap in the metal pattern, and wherein an etching gas used to form the metal pattern remains in the gap in the metal pattern,
- and
- a barrier pattern on a sidewall and a lower surface of the metal pattern, and
- a capping pattern contacting an upper surface of the through via, the capping pattern including a lowermost edge portion of the capping pattern, the lowermost edge portion is not higher than a lowermost surface of a central portion of the capping pattern.
9 more elements
Dependencies are inferred from the claim text.