Semiconductor device

A semiconductor device comprising:

• gate electrodes spaced apart from each other on a substrate and stacked in a direction perpendicular to an upper surface of the substrate;
• and
• channel structures that extend through the gate electrodes,
• wherein ones of the channel structures comprise a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer on a side surface of the channel insulating layer and on at least a portion of a side surface of the pad layer,
• wherein the channel layer comprises a first channel region on the side surface of the channel insulating layer, and a second channel region on the first channel region,
• wherein the second channel region is adjacent to a first erase gate electrode that is a farthest one of the gate electrodes from the substrate,
• wherein the second channel region overlaps at least a portion of the side surface of the pad layer,
• wherein the second channel region comprises a semiconductor material doped with a first conductivity type impurity, the first channel region comprises a semiconductor material having an impurity concentration lower than an impurity concentration in the second channel region, and the pad layer comprises a semiconductor material doped with a second conductivity type impurity that is different from the first conductivity type impurity, and
• wherein the second channel region and the pad layer are configured to form a P-N junction therebetween.

A semiconductor device comprising:

• gate electrodes spaced apart from each other on a substrate and stacked in a first direction perpendicular to an upper surface of the substrate;
• a conductive layer between the substrate and the gate electrodes;
• channel structures extending in the first direction, that extend through the gate electrodes, and extend into at least a portion of the substrate;
• and
• a separation region that extends through the gate electrodes and extends in the first direction,
• wherein ones of the channel structures comprise a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer on a side surface of the channel insulating layer and on at least a portion of a side surface of the pad layer,
• wherein the conductive layer is in contact with the channel layer of the ones of the channel structures in a direction parallel to the upper surface of the substrate,
• wherein the channel layer comprises a first channel region and a second channel region overlapping at least a portion of the pad layer in a direction parallel to the upper surface of the substrate,
• wherein the second channel region comprises a first conductivity type impurity and the pad layer comprises a second conductivity type impurity,
• wherein the second channel region is in contact with the pad layer to form a P-N junction between the second channel region and the pad layer, and
• wherein at least a portion of the second channel region overlaps an erase gate electrode that is in an uppermost portion of the gate electrodes in a direction parallel to the upper surface of the substrate.