US 11,903,195 B2Granted

Openings layout of three-dimensional memory device

AssigneeYangtze Memory Technologies Co., Ltd.

InventorsJia He, Haihui Huang, Fandong Liu, Yaohua Yang, Peizhen Hong, Zhiliang Xia, Zongliang Huo, Yaobin Feng, Baoyou Chen, Qingchen Cao

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Abstract

Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Claims19

Dependent claims

A semiconductor structure, comprising:

a stack structure comprising a plurality of conductor layers and a plurality of insulating layers stacking alternately along a direction perpendicular to a top surface of the stack structure;
and
an array of semiconductor channels within a first region of the stack structure, wherein each semiconductor channel of the array of semiconductor channels penetrates through the stack structure, and wherein:
the array of semiconductor channels comprises:
semiconductor channels in a first row and adjacent to a second region of the stack structure, wherein the second region is adjacent to the first region;
and
semiconductor channels in a second row farther away from the second region than the semiconductor channels in the first row;
a first length of a top surface of each of the semiconductor channels in the first row is greater than a second length of a top surface of each of the semiconductor channels in the second row, wherein the first length and the second length are along a first direction parallel to the top surface of the stack structure and pointing from the second region to the first region;
the first length of the top surface of each of the semiconductor channels in the first row is greater than a first width of the top surface of each of the semiconductor channels in the first row, wherein the first width is along a second direction parallel to the top surface of the stack structure and perpendicular to the first direction;
and
the second length of the top surface of each of the semiconductor channels in the second row is substantially the same as a second width of the top surface of each of the semiconductor channels in the second row, wherein the second width is along the second direction.

8 more elements

A semiconductor structure, comprising:

a stack structure comprising a plurality of conductor layers and a plurality of insulating layers stacking alternately along a direction perpendicular to a top surface of the stack structure;
and
an array of semiconductor channels within a first region of the stack structure, wherein each semiconductor channel of the array of semiconductor channels penetrates through the stack structure, wherein:
the array of semiconductor channels comprises:
semiconductor channels in a first row and adjacent to a second region of the stack structure, wherein the second region is adjacent to the first region;
and
semiconductor channels in one or more rows farther away from the second region than the semiconductor channels in the first row;
a distance L1 between a first semiconductor channel in the first row and a second semiconductor channel in a second row adjacent to the first row is greater than a distance L2 between the second semiconductor channel in the second row and a third semiconductor channel in a third row adjacent to the second row, wherein the second semiconductor channel is adjacent to the first semiconductor channel and the third semiconductor channel;
and
the distance L2 is greater than a distance L3 between the third semiconductor channel and a fourth semiconductor channel in a fourth row adjacent to the third row, wherein the fourth semiconductor channel is adjacent to the third semiconductor channel.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/156,619Filed 19 Jan 2023 · continuation
Priority: CN 201710134033.97 Mar 2017
Published: US 2023/0157020 A118 May 2023
Granted: 13 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 43/20
EEPROM devices comprising charge-trapping gate insulators: characterised by three-dimensional [3D] arrangements, e.g. with cells on different…
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Family

PCT/CN2018/077716Parent of this continuation · filed 1 Mar 2018
Application16/046,475Parent of this division · filed 26 Jul 2018
Application17/017,417Parent of this continuation · filed 10 Sep 2020
US 10,804,283 B2Parent of this division · filed 13 Oct 2020
US 2023/0157020 A1Pre-grant publication · published 18 May 2023
US 11,574,919 B2Parent of this continuation
Application17/017,417Parent of this division
Application16/046,475Parent of this continuation
US 2019/0013327 A1Published application
US 2021/0151458 A1Published application
US 11,903,195 B2This patent

From the US filing history. Foreign family members aren’t listed.