Integrated circuit
AssigneeMacronix International Co., Ltd.
InventorYa-Chun Tsai
Life of this patent
Estimating the term…
Abstract
In one embodiment of this disclosure, an integrated circuit includes at least one first memory block, at least one second memory block, and a pad disposing area. The first memory block and the second memory block are respectively disposed at two sides of the integrated circuit, wherein each of the first memory block and the second memory block includes a memory cell array having a three-dimension structure. The first memory block and the second memory block are symmetrically disposed about the pad disposing area. A plurality of pads are disposed in the pad disposing area. The pads are respectively electrically coupled to the first memory block and the second memory block.
Claims14
An integrated circuit, comprising:
- at least one first memory block and at least one second memory block respectively disposed on two sides of the integrated circuit, wherein each of the at least one first memory block and the at least one second memory block includes a memory cell array having a three-dimensional architecture;
- and
- a pad disposing area, wherein the at least one first memory block and the at least one second memory block are symmetrically disposed about the pad disposing area, a plurality of pads are disposed in the pad disposing area, and the pads are respectively electrically coupled to the at least one first memory block and the at least one second memory blocks,
- wherein each of the at least one first memory block and the at least one second memory block comprises a control circuit generating a control signal to control an access operation of the corresponding memory cell array,
- wherein the control circuit of the at least one first memory block and the control circuit of the at least one second memory block are symmetrically disposed about the pad disposing area.
An integrated circuit, comprising:
- two adjacent first memory blocks and two adjacent second memory blocks respectively disposed on two sides of the integrated circuit, wherein each of the two first memory blocks and the two second memory blocks comprises a memory cell array having a three-dimensional architecture and a shortest spacing distance between the memory cell array of the two adjacent first memory blocks;
- and
- a pad disposing area disposed between the two adjacent first memory blocks and the two adjacent second memory blocks, wherein a plurality of pads are disposed in the pad disposing area, and the pads are respectively electrically coupled to the two adjacent first memory blocks and the two adjacent second memory blocks,
- wherein each of the two adjacent first memory block comprises a first control circuit generating a first control signal to control an access operation of the corresponding first memory cell array, each of the two adjacent second memory block comprises a second control circuit generating a second control signal to control an access operation of the corresponding second memory cell array, and the two first control circuits and the second control circuits are symmetrically disposed about the pad disposing area.
Dependencies are inferred from the claim text.