Two dimensional structure to control flash operation and methods for forming the same

A method of making a MOSFET device, the method comprising:

• forming a first floating gate trench in a substrate;
• forming a first tunnel dielectric layer on sidewalls of the first floating gate trench;
• forming a first floating gate electrode in the first floating gate trench on the first tunnel dielectric layer;
• forming a continuous control gate dielectric layer over a top surface of the floating gate electrode;
• forming a control gate layer over a top surface of the control gate dielectric layer;
• patterning the control gate layer and the continuous control gate dielectric layer, wherein patterned portions of the control gate layer and the continuous control gate dielectric layer comprise a first control gate electrode and a first control gate dielectric layer;
• forming a first sidewall spacer on the first control gate dielectric layer and the first control gate electrode;
• and
• forming a source region and drain region within an upper portion of the substrate, wherein a channel region continuously extends between the source region and the drain region underneath the first floating gate trench, a first p-n junction between the channel region and the source region has a first top edge that is aligned to, and adjoined to, a bottom edge a first outer sidewall of the first sidewall spacer, and a second p-n junction between the channel region and the drain region has a second top edge that is aligned to, and adjoined to, a bottom edge a second outer sidewall of the first sidewall spacer, wherein the source region and the drain region are laterally spaced from, and do not directly contact, the tunnel dielectric layer.

A method of forming a semiconductor device, the method comprising:

• forming a first floating gate trench and a second floating gate trench in an upper portion of a substrate, wherein the first floating gate trench has a first depth and the second floating gate trench has a second depth that is different from the first depth;
• forming a first tunnel dielectric layer on a bottom surface of the first floating gate trench and a second tunnel dielectric layer on a bottom surface of the second floating gate trench;
• forming a first floating gate electrode in the first floating gate trench on the first tunnel dielectric layer and forming a second floating gate electrode in the second floating gate trench on the second tunnel dielectric layer;
• forming a first control gate dielectric layer on the first floating gate electrode and forming a second control gate dielectric layer on the second floating gate electrode;
• and
• forming a first control gate electrode on the first control gate dielectric layer and forming a second control gate electrode on the second control gate dielectric layer.