Semiconductor device and method of manufacturing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJosh Lin, Chia-Ta Hsieh, Chen-Ming Huang, Chi-Wei Ho
Life of this patent
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Abstract
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first gate structure over a substrate and laterally surrounded by a first sidewall spacer. The first gate structure protrudes outward from a top of the first sidewall spacer. A second gate structure is over the substrate and is laterally surrounded by a second sidewall spacer. The first gate structure has a first height that is larger than a second height of the second gate structure. The first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.
Claims20
An integrated chip, comprising:
- a first gate structure over a substrate and laterally surrounded by a first sidewall spacer, wherein the first gate structure protrudes outward from a top of the first sidewall spacer;
- a second gate structure over the substrate and laterally surrounded by a second sidewall spacer that extends to a top of the second gate structure, wherein the first gate structure has a first height that is larger than a second height of the second gate structure;
- and
- wherein the first sidewall spacer has a first cross-sectional profile that is a different shape and a different size than a second cross-sectional profile of the second sidewall spacer.
An integrated chip, comprising:
- a first gate structure disposed over a substrate and laterally surrounded by a first sidewall spacer, wherein the first gate structure protrudes outward from a top of the first sidewall spacer;
- a second gate structure disposed over the substrate and laterally surrounded by a second sidewall spacer, wherein the second gate structure protrudes outward from a top of the second sidewall spacer;
- a dielectric material disposed over the first gate structure and the second gate structure, wherein the dielectric material continuously extends from over the first sidewall spacer to directly between the first sidewall spacer and the second sidewall spacer;
- an etch stop layer continuously extending from along a sidewall of the first sidewall spacer to along a sidewall of the first gate structure that is over the top of the first sidewall spacer, wherein interior sidewalls of the etch stop layer facing the first gate structure are steeper along the sidewall of the first gate structure than along the sidewall of the first sidewall spacer;
- and
- a conductive contact extending from an upper surface of the dielectric material to contact the first gate structure, the conductive contact having a bottommost surface that contacts the first gate structure vertically above the top of the first sidewall spacer.
An integrated chip, comprising:
- a first gate structure over a substrate;
- a first sidewall spacer arranged along opposing sides of the first gate structure, wherein the first gate structure protrudes outward from a top of the first sidewall spacer;
- a conductive contact disposed on the first gate structure, wherein the top of the first sidewall spacer is a non-zero distance below a bottom of the conductive contact;
- a second gate structure over the substrate;
- a second sidewall spacer arranged along opposing sides of the second gate structure, wherein the second gate structure protrudes outward from a top of the second sidewall spacer;
- and
- wherein lines extending along substantially linear segments of the first sidewall spacer and the second sidewall spacer intersect to define a “V” shape as viewed in a cross-sectional view.
Dependencies are inferred from the claim text.