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US 11,903,191 B2Granted
Embedded flash memory device with floating gate embedded in a substrate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei Cheng Wu, Harry-Hak-Lay Chuang
Life of this patent
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Abstract
An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.
Claims20
A method comprising:
- recessing a portion of a semiconductor substrate in a first region of the semiconductor substrate to form a recess;
- depositing a bottom dielectric layer over the semiconductor substrate and along a bottom surface of the recess;
- forming a charge storage layer over the bottom dielectric layer, wherein a portion of the charge storage layer is in the recess and below a top surface of the semiconductor substrate;
- performing a planarization to give the charge storage layer and the bottom dielectric layer level top surfaces;
- forming a first dielectric layer over and physically contacting the charge storage layer;
- forming a second dielectric layer over a second region of the semiconductor substrate, wherein after forming the first dielectric layer and after forming the second dielectric layer:
- the second region is free of the first dielectric layer;
- and
- the first region is free of the second dielectric layer;
- forming a third dielectric layer over the first dielectric layer and the second dielectric layer;
- after forming the third dielectric layer, patterning the first dielectric layer and the second dielectric layer to form a first stack of layers directly above the recess and a second stack of layers directly above the second region of the semiconductor substrate;
- and
- forming a metal layer over the first dielectric layer in the first region and over the second dielectric layer in the second region, wherein after patterning and after forming the metal layer, a first portion of the metal layer comprises a first gate electrode directly above the recess and a second portion of the metal layer comprises a second gate electrode directly above the second region of the semiconductor substrate.
10 more elements
A method comprising:
- recessing a semiconductor portion of a semiconductor substrate to form a recess in a memory array region of the semiconductor substrate, the semiconductor substrate having an upper surface in a non-recessed region of the semiconductor substrate, wherein a bottom surface of the recess is a surface of the semiconductor substrate;
- depositing a bottom dielectric layer on the bottom surface of the recess;
- forming a charge storage layer over the bottom dielectric layer, wherein a portion of the charge storage layer is in the recess;
- planarizing the charge storage layer and the bottom dielectric layer;
- forming a top dielectric layer over and physically contacting the charge storage layer and the bottom dielectric layer, the top dielectric layer being above the upper surface of the semiconductor substrate;
- forming a high-k dielectric layer over the top dielectric layer, wherein after forming the high-k dielectric layer, the top dielectric layer is above a topmost surface of the bottom dielectric layer;
- forming a conductive gate over the high-k dielectric layer;
- and
- forming a source region and a drain region in the semiconductor substrate and on opposite sides of the bottom dielectric layer to form a memory device, wherein an array of memory devices is formed in the memory array region when the memory device is formed.
6 more elements
A method comprising:
- etching a recess into a semiconductor substrate;
- blanket depositing a bottom dielectric layer in the recess and over a non-recessed portion of the semiconductor substrate;
- forming a charge storage layer over the bottom dielectric layer, wherein a first portion of the charge storage layer is in the recess and a second portion of the charge storage layer is over the non-recessed portion of the semiconductor substrate;
- planarizing the bottom dielectric layer and the charge storage layer, after planarizing the charge storage layer being level with and directly interposing two sidewall portions of the bottom dielectric layer;
- forming a top dielectric layer over and physically contacting the charge storage layer;
- forming a silicon oxide layer over and physically contacting the non-recessed portion of the semiconductor substrate;
- forming a first dielectric layer over and physically contacting the top dielectric layer and the silicon oxide layer;
- and
- patterning to form a first stack and a second stack, the patterning removing a first horizontal portion of the bottom dielectric layer, the first stack comprising first portions of the bottom dielectric layer, the charge storage layer, and the first dielectric layer, the second stack comprising second portions of the silicon oxide layer and the first dielectric layer.
6 more elements
Dependencies are inferred from the claim text.