Three-dimensional memory and fabricating method thereof

A three-dimensional memory, comprising:

• a memory cell array comprising a plurality of levels stacked in a first direction, wherein a plurality of memory cells are formed in a plurality of lines in each of the levels, wherein each of the memory cells comprises a transistor, and the transistor comprises:
• a first isolation region and a second isolation region formed in a lower layer of the level, wherein the first isolation region is separated from the second isolation region by a first memory film in the lower layer;
• a drain region and a source region formed in a middle layer of the level, wherein the drain region is separated from the source region by a second memory film in the middle layer, and a channel between the drain region and source region is wrapped by the second memory film;
• a first electrode and a second electrode formed in a higher layer of the level, wherein the first electrode is separated from the second electrode by a third memory film in the higher layer;
• and
• a gate electrode formed between the source region and drain region, wherein the first, second, and third memory films are wrapped by the gate electrode,
• wherein the channels and the gate electrodes of the transistors in the memory cells of two adjacent lines in the same level are staggered.

A three-dimensional memory, comprising:

• a plurality of memory cells arranged in a plurality of levels stacked in a first direction, and divided into a plurality of groups, wherein each of the groups of the memory cells is formed in respective level of the levels;
• a plurality of bit lines, wherein each of the bit lines comprises a plurality of sub-bit lines, and each of the sub-bit lines is formed in respective level of the levels;
• a plurality of source lines, wherein each of the source lines comprises a plurality of sub-source lines, and each of the sub-source lines is formed in respective level of the levels;
• and
• a plurality of word lines extending along a second direction and formed in the same layer different from the levels, wherein top surfaces of the word lines are lower than the memory cells, the sub-bit lines, and the sub-source lines, wherein the second direction is perpendicular to the first direction,
• wherein in each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged and separated from each other by the memory cells of the columns.