Vertical memory device
AssigneeSK hynix Inc.
InventorsKun-Young Lee, Sun-Young Kim
Life of this patent
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Abstract
Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line.
Claims11
A method for fabricating a memory device, comprising:
- forming a bit line extending vertically from a peripheral circuit portion;
- forming a capacitor surrounding the bit line;
- forming a transistor including a vertical active layer extending vertically from a first side of the capacitor and a word line surrounding the vertical active layer;
- and
- forming a plate line coupled to a second side of the capacitor, and extending vertically from the peripheral circuit portion,
- wherein the forming of the transistor comprises:
- forming a first source/drain layer coupled to the first side of the capacitor;
- forming a vertical channel layer epitaxial-grown vertically from the first source/drain layer;
- and
- forming a second source/drain layer epitaxial-grown horizontally from the vertical channel layer, and coupled to the bit line.
Dependencies are inferred from the claim text.