Pixel sensor having hierarchical memory

An apparatus comprising:

• an array of pixel cells, each pixel cell including:
• a photodiode to generate a charge in response to incident light,
• a charge sensing unit configured to generate a voltage based on the charge, and
• an in-pixel memory configured to store a digital output generated by a quantizer based on quantizing the voltage;
• a bus interface;
• an off-array frame memory connected to the bus interface and the array of pixel cells, the in-pixel memory of the array of pixel cells being connected to the frame memory via a set of parallel interconnects;
• and
• a frame memory controller configured to:
• control the frame memory to receive, via the set of parallel interconnects, the digital outputs from the in-pixel memory of each pixel cell of the array of pixel cells;
• store the digital outputs in the frame memory;
• fetch the digital outputs from the frame memory;
• and
• transmit the digital outputs to a host device via the bus interface.