Analog-to-digital converter or digital-to-analog converter data path with deterministic latency
AssigneeIntel Corporation
InventorsDan Pritsker, Colman Cheung, Benjamin Esposito
Life of this patent
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Abstract
A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.
Claims20
A circuit system comprising:
- an analog-to-digital converter circuit;
- a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit;
- and
- a variable latency circuit coupled to a first data path comprising the digital-to-analog converter circuit, wherein the variable latency circuit generates a deterministic latency in a first output signal that is based on a first difference between a maximum latency of the first data path and a measured latency of the first data path.
A circuit system comprising:
- an analog-to-digital converter circuit;
- a measurement circuit that generates a first measurement of a first latency of a first data path that comprises the analog-to-digital converter circuit;
- and
- a first variable latency circuit coupled to the first data path, wherein the first variable latency circuit generates a delayed signal that is delayed relative to an input signal, and wherein the first variable latency circuit causes the delayed signal to have a first deterministic latency that is based on a difference between a maximum latency of the first data path and the first measurement of the first latency of the first data path.
A method for generating a deterministic latency for a first data path that comprises a digital-to-analog converter circuit, the method comprising:
- measuring a second latency of a second data path through the first data path and a third data path, wherein the third data path comprises an analog-to-digital converter circuit;
- determining a third latency of the first data path using a variable latency circuit based on a first difference between the second latency of the second data path and a fourth latency of the third data path;
- and
- generating the deterministic latency in a first output signal of the variable latency circuit based on a second difference between a maximum latency of the first data path and the third latency of the first data path.
Dependencies are inferred from the claim text.