Analog channel equalization and channel adaptation

A method comprising:

• generating, using a front-end circuit, a filtered signal, wherein generating the filtered signal comprises performing filtering of an incoming signal that includes a stream of data symbols;
• generating, using a summing circuit, an equalized signal, wherein generating the equalized signal comprises the summing circuit combining the filtered signal and a feedback signal;
• generating, using a sample recovery circuit, a plurality of recovered data symbols by sampling the equalized signal;
• generating the feedback signal, using a decision feedback equalization circuit, based on the plurality of recovered data symbols;
• and
• causing adjustment to one or more filters in the front-end circuit, using a logic circuit, based on the plurality of recovered data symbols, wherein the logic circuit comprises a finite state machine, and wherein the method further comprises the finite state machine generating control signals to cause adjustment to one or more resistances and one or more capacitances in the filters of the front-end circuit.

A system comprising:

• a receiver circuit configured to receive, from a transmitter, an incoming signal having a stream of data symbols, wherein the receiver circuit includes:
• a continuous time linear equalizer (CTLE) circuit configured to generate a filtered signal based on the incoming signal;
• a summing circuit configured to generate an equalized signal by combining the filtered signal with a feedback signal;
• a sample recovery circuit configured to recover a plurality of symbols from the equalized signal;
• a decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered symbols;
• and
• a finite state machine configured to cause adjustments to one or more filters in the CTLE circuit based on the plurality of recovered symbols, wherein the one or more filters include one or more resistances and one or more capacitances, and wherein the finite state machine is configured to generate control signals to cause adjustments of the one or more filters by adjusting the one or more resistances and the one or more capacitances.