Analog front-end receiver and electronic device including the same

An analog front-end receiver comprising:

• a terminating resistor provided between a first node, to which a first data line is electrically connected, and a second node, to which a second data line is electrically connected, the terminating resistor being configured to receive a first differential signal from the first data line via the first node, and configured to receive a second differential signal from the second data line via the second node, the second differential signal being differential from the first differential signal;
• a first equalizer configured to, in a first operation mode, block the first differential signal provided through the first node, and configured to, in a second operation mode, output a first equalization differential signal corresponding to the first differential signal to a third node without blocking the first differential signal, the second operation mode being different from the first operation mode;
• a second equalizer configured to, in the first operation mode, block the second differential signal provided through the second node, and configured to, in the second operation mode, output a second equalization differential signal corresponding to the second differential signal to a fourth node without blocking the second differential signal;
• and
• a common mode voltage generator including a first current source electrically connected to the third node and a second current source electrically connected to the fourth node,
• wherein the first current source is configured to provide a current to the first equalizer to provide a first common mode voltage to the third node, and the second current source is configured to provide a current to the second equalizer to provide a second common mode voltage to the fourth node.

An electronic device comprising:

• a physical layer configured to receive a first differential signal and a second differential signal that are differential from each other through an external interface, and configured to output digital data corresponding to the first differential signal and the second differential signal;
• a link layer configured to output a control signal based on the digital data;
• and
• a driving device in which a program is executed based on the control signal,
• wherein the physical layer includes:
• a first equalizer configured to, in a first operation mode, block the first differential signal provided through a first node, and configured to, in a second operation mode, output a first equalization differential signal corresponding to the first differential signal without blocking the first differential signal, the second operation mode being different from the first operation mode;
• a second equalizer configured to, in the first operation mode, block the second differential signal provided through a second node, and configured to, in the second operation mode, output a second equalization differential signal corresponding to the second differential signal without blocking the second differential signal;
• a terminating resistor provided between the first node and the second node, and configured to receive the first differential signal through the first node, and configured to receive the second differential signal through the second node;
• and
• a low pass filter configured to receive a third differential signal converted by the terminating resistor from the first differential signal, and to receive a fourth differential signal converted by the terminating resistor from the second differential signal,
• wherein in the second operation mode, the low pass filter is turned off to block outputs corresponding to the third differential signal and the fourth differential signal.