Low-density parity-check (LDPC) encoding method and apparatus

A low-density parity-check (LDPC) decoding method, wherein the method comprises:

• obtaining, by a receive end, an encoded first codeword;
• and
• decoding, by the receive end, the encoded first codeword based on a first check matrix, wherein a code length of the encoded first codeword is (n+j×Z), and the encoded first codeword comprises k information bits and (n—k+j×Z) redundant bits, wherein:
• the first check matrix is a submatrix of the first ((n—k)/Z+j) rows and the first (n/Z+j) columns in a check matrix H, and a code rate of the first check matrix is equal to a first transmission code rate;
• n is an integer greater than 0, j is an integer greater than or equal to 0, and Z is an integer greater than 0;
• the check matrix H is a matrix of ((n—k)/Z+Q) rows and (n/Z+Q) columns, Q is an integer greater than or equal to j, each element in the check matrix H represents one Z×Z square submatrix, and the square submatrix is a cyclic permutation matrix of an identity matrix or an all-zero matrix;
• the check matrix H comprises a matrix HMC, a matrix HIR of Q rows and 24 columns, an all-zero matrix of 4 rows and Q columns, and an identity matrix of Q rows and Q columns;
• and
• the matrix HMC is a matrix of (n—k)/Z rows and n/Z columns, the matrix HMC is located at an upper left corner of the check matrix H, the matrix HIR of Q rows and 24 columns is located at a lower left corner of the check matrix H, the all-zero matrix of 4 rows and Q columns is located at an upper right corner of the check matrix H, and the identity matrix of Q rows and Q columns is located at a lower right corner of the check matrix H.

A transmit end, wherein the transmit end comprises:

• at least one processor;
• and
• one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to obtain k information bits to be sent to a receive end, and perform low-density parity-check (LDPC) encoding on the k information bits by using a first check matrix based on a first transmission code rate R satisfying R=k/(n+j×Z) to obtain a first codeword, wherein:
• k is an integer greater than 0;
• the first check matrix is a submatrix of the first ((n-k)/Z+j) rows and the first (n/Z+j) columns in a check matrix H, and a code rate of the first check matrix is equal to the first transmission code rate;
• n is an integer greater than 0, j is an integer greater than or equal to 0, and Z is an integer greater than 0;
• the check matrix H is a matrix of ((n-k)/Z+Q) rows and (n/Z+Q) columns, Q is an integer greater than or equal to j, each element in the check matrix H represents one Z×Z square submatrix, and the square submatrix is a cyclic permutation matrix of an identity matrix or an all-zero matrix;
• the check matrix H comprises a matrix HMC, a matrix HIR of Q rows and 24 columns, an all-zero matrix of 4 rows and Q columns, and an identity matrix of Q rows and Q columns;
• and
• the matrix HMCis a matrix of (n-k)/Z rows and n/Z columns, the matrix HMCis located at an upper left corner of the check matrix H, the matrix HIR of Q rows and 24 columns is located at a lower left corner of the check matrix H, the all-zero matrix of 4 rows and Q columns is located at an upper right corner of the check matrix H, and the identity matrix of Q rows and Q columns is located at a lower right corner of the check matrix H;
• and
• a transmitter, the transmitter configured to send the first codeword to the receive end, wherein the first codeword comprises the k information bits and (n-k+j×Z) redundant bits.

A receive end, wherein the receive end comprises:

• at least one processor;
• and
• one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to obtain an encoded first codeword and decode the encoded first codeword based on a first check matrix, wherein a code length of the encoded first codeword is (n+j×Z), and the encoded first codeword comprises k information bits and (n—k+j×Z) redundant bits, wherein:
• the first check matrix is a submatrix of the first ((n—k)/Z+j) rows and the first (n/Z+j) columns in a check matrix H, and a code rate of the first check matrix is equal to a first transmission code rate;
• n is an integer greater than 0, j is an integer greater than or equal to 0, and Z is an integer greater than 0;
• the check matrix H is a matrix of ((n—k)/Z+Q) rows and (n/Z+Q) columns, Q is an integer greater than or equal to j, each element in the check matrix H represents one Z×Z square submatrix, and the square submatrix is a cyclic permutation matrix of an identity matrix or an all-zero matrix;
• the check matrix H comprises a matrix HMC, a matrix HIR of Q rows and 24 columns, an all-zero matrix of 4 rows and Q columns, and an identity matrix of Q rows and Q columns;
• and
• the matrix HMC is a matrix of (n—k)/Z rows and n/Z columns, the matrix HMC is located at an upper left corner of the check matrix H, the matrix HIR of Q rows and 24 columns is located at a lower left corner of the check matrix H, the all-zero matrix of 4 rows and Q columns is located at an upper right corner of the check matrix H, and the identity matrix of Q rows and Q columns is located at a lower right corner of the check matrix H.