Error correction coding apparatus and error correction decoding apparatus
AssigneeMitsubishi Electric Corporation
InventorsHideo Yoshida, Tsuyoshi Yoshida, Yoshiaki Konishi, Kenji Ishii
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Abstract
An error correction coding apparatus that performs error correction coding using, as an error correction code sequence, a frame of m bits×n symbols input in m-bit parallel, where m and n are positive integers, includes: an error correction coding circuit that performs error correction coding using, as information bits, m bits×n symbols including known bits assigned to a bit sequence specified in the error correction code sequence and generate error correction coded parity bits; and a selector that replaces the known bits of the error correction code sequence with the parity bits.
Claims6
An error correction decoding apparatus to perform error correction decoding, the apparatus comprising:
- a parity bit syndrome circuit to perform a syndrome operation of parity bits included in a multilevel modulation symbol, the multilevel modulation symbol having being error correction coded by the error correction coding apparatus using, as an error correction code sequence, a frame of m bits×n parallel symbols defining a multilevel symbol and input in m-bit parallel where m and n are positive integers, the parity bits being error correction coded, the error correction coding apparatus replacing known bits assigned to a bit sequence specified in the error correction code sequence, with the parity bits, the multilevel modulation symbol being input in m-bit parallel;
- an information bit syndrome circuit to perform a syndrome operation of information bits and the known bits included in the multilevel modulation symbol, the known bits replacing the parity bits included in the multilevel modulation symbol;
- and
- an error correction decoding circuit to perform error correction decoding, using syndrome data calculated by the parity bit syndrome circuit and the information bit syndrome circuit.
Dependencies are inferred from the claim text.