Memory controller and method of accessing flash memory
AssigneeSilicon Motion, Inc.
InventorsShiuan-Hao Kuo, Zhen-U Liu
Life of this patent
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Abstract
A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.
Claims12
A memory controller, for use in a data storage device, wherein a low-density parity check (LDPC) process performed by the memory controller comprises an initial phase, a decoding phase, and an output phase, the memory controller comprising:
- a variable-node circuit;
- and
- a check-node circuit,
- wherein during the initial phase, the variable-node circuit performs the following steps:
- obtaining a channel value, that is read from a flash memory, from a channel-value memory;
- transmitting the channel value to the check-node circuit to calculate a syndrome;
- and
- in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory to 0, and entering the decoding phase;
- wherein in the decoding phase, during each LDPC decoding iterative operation, the variable-node circuit performs the following steps:
- calculating a syndrome weight according to the syndrome;
- obtaining one or more first codeword bits in the previous codeword with the value of the register being 1 from the variable-node memory, and regarding other second codeword bits in the previous codeword as 0;
- performing a bit-flipping algorithm according to the syndrome weight to flip one or more codeword bits in the first codeword bits and the second codeword bits in the previous codeword to generate an updated codeword;
- subtracting the previous codeword from the updated codeword to generate a codeword difference;
- and
- transmitting the codeword difference to the check-node circuit to update the syndrome.
A method of accessing a flash memory, for use in a memory controller of a data storage device, wherein a low-density parity check (LDPC) process performed by the memory controller comprises an initial phase, a decoding phase, and an output phase, the method comprising:
- storing data to the flash memory of the data storage device via a storage procedure;
- wherein during the initial phase, the method comprises:
- obtaining a channel value, that is read from a flash memory, from a channel-value memory;
- transmitting the channel value to the check-node circuit to calculate a syndrome;
- and
- in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory to 0, and entering the decoding phase;
- wherein the method further comprises:
- in response to the value of the register in the variable-node memory corresponding to a specific bit in a decoding result being 0, setting the channel value to the specific bit;
- and
- in response to the value of the register in the variable-node memory corresponding to the specific bit of the decoding result being 1, calculating the specific bit by performing an XOR operation on the channel value and the variable-node symbol value corresponding to the specific bit.
Dependencies are inferred from the claim text.