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US 11,901,905 B2Granted
Receiver side setup and hold calibration
AssigneeSanDisk Technologies LLC
InventorTianyu Tang
Life of this patent
Estimating the term…
Abstract
The present disclosure provides for calibrating clock signals in an unmatched data input system. In various embodiments, an unmatched data input system uses multi-delay circuits to calibrate a clock signal distributed to various input/outputs in the unmatched data input system. These multi-delay circuits can include coarse delay circuits and fine delay circuits that provide a broad range as well as accurate delay capabilities. Through the use of these multi-delay circuits, the unmatched data input system can optimally align a clock signal with its associated data signal across multiple input/outputs.
Claims20
A method comprising:
- receiving, by a system, a data signal;
- storing, by the system, the data signal as a latched data signal;
- receiving, by the system, a clock signal;
- based on the received clock signal, providing a set of local clock signals to a set of input/outputs (IO);
- calibrating, by the system, the local clock signals for each IO of the set of IOs based on the latched data signal, wherein the calibrating comprises:
- determining, for each IO of the set of IOs, a delay to apply to a respective local clock signal of local clock signals based on the latched data signal to align clock edges of the set of local clock signals;
- and
- delaying the local clock signal for each IO of the set of IOs;
- calibrating, by the system, the latched data signal based on the calibrated local clock signals;
- and
- processing, by the system, the calibrated data signal based on the calibrated local clock signals.
8 more elements
An apparatus, comprising:
- an interface for receiving a data signal and receiving a clock signal;
- a set of input/outputs (IOs) connected to the interface along a set of clock paths, wherein the set of clock paths communicate a set of local clock signals to the set of IOs based on the received clock signal;
- and
- a controller in communication with the interface and the set of IOs, wherein the controller causes the apparatus to perform:
- receiving a data signal on the interface;
- storing the received data signal as a latched data signal;
- receiving a clock signal on the interface;
- calibrating the local clock signals for each latch circuit of the set of latch circuits based on the latched data signal, wherein the calibrating comprises:
- determining, for each IO of the set of IOs, a delay to apply to a respective local clock signal of the set of local clock signals based on the latched data signal to align clock edges of the set of local clock signals;
- and
- delaying the local clock signal for each IO of the set of IOs;
- calibrating the latched data signal based on the calibrated local clock signals;
- and
- processing the calibrated data signal based on the calibrated local clock signals.
11 more elements
A system comprising:
- a set of data signal input circuits configured to receive a data signal and store the received data signal as a latched data signal;
- a clock signal input circuit configured to receive a clock signal;
- a set of clock paths that connect the clock signal input circuit to the set of data signal input circuits;
- a set of input/output (IO) circuits on the clock paths between the data signal input circuit and the clock signal input circuit, the set of IO circuits are configured to receive, via the set of clock paths, local clock signals at different timings based a clock signal received at the clock signal input circuit;
- and
- a set of multi-delay circuits that on the set of clock paths and connected between the set of data signal input circuits and the clock signal input circuit, each multi-delay circuit of the set of multi-delay circuits includes a first delay circuit that delays a respective local clock signal by a first delay time and a second delay circuit that delays the respective local clock signal by a second delay time, wherein the second delay time is shorter than the first delay time, wherein the set of multi-delay circuits are calibrated to apply the first and second delay time to the local clock signal for each IO circuit of the set of IO circuits based on the latched data signal to align clock edges of the set of local clock signals.
3 more elements
Dependencies are inferred from the claim text.