Integrated circuit including flip-flop and computing system for designing the integrated circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsSeungman Lim, Minsu Kim, Ahreum Kim
Life of this patent
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Abstract
An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.
Claims16
An integrated circuit comprising:
- a first flip-flop configured to operate in synchronization with a clock signal, wherein the first flip-flop includes,
- a multiplexer configured to receive a scan enabled signal, a scan input signal, a data input signal, and a reset input signal, the multiplexer configured to output an inverted signal of the scan input signal to a first node based on the scan enable signal, the multiplexer configured to output an inverted signal of the data input signal or a signal having a first level to the first node based on the reset input signal, the multiplexer configured to selectively output the inverted signal of the scan input signal, the inverted signal of the data input signal, or the signal having the first level to the first node based on the reset input signal and the scan enable signal,
- a master latch configured to latch the output signal through the first node, and to output the latched signal, and
- a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.
An integrated circuit comprising:
- a first flip-flop configured to operate in synchronization with a clock signal, wherein the first flip-flop includes,
- a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, the multiplexer configured to output an inverted signal of a data input signal a signal having a first level to the first node based on a reset input signal,
- a master latch configured to latch the output signal through the first node, and to output the latched signal, and
- a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch, wherein the multiplexer comprises:
- first and second n-type field-effect transistors (NFETs) connected in series to each other, the first and second NFETs between a ground node and the first node, the first NFET configured to receive the scan enable signal and the second NFET configured to receive the scan input signal;
- and
- third to fifth NFETs connected in series to each other, the third to fifth NFETs between the first node and the ground node, the third NFET configured to receive an inverted scan enable signal provided by inverting the scan enable signal, the fourth NFET configured to receive the data input signal, and the fifth NFET configured to receive the reset input signal.
Dependencies are inferred from the claim text.