Back to results
US 11,901,869 B2Granted
Amplifier capable of minimizing short-circuit current of output stage while having improved slew rate
AssigneeDB HiTek Co., Ltd.
InventorsMun Gyu Kim, Yong In Park
Life of this patent
Estimating the term…
Abstract
Disclosed is an amplifier capable of minimizing shortcircuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.
Claims17
An amplifier comprising:
- an input unit configured to receive a differential input signal at a first input terminal and a second input terminal;
- a conversion unit comprising a first current mirror comprising a first current determiner and a first current follower configured to operate in response to a voltage or current on a first current determination and/or voltage generation node of the first current determiner, a second current mirror comprising a second current determiner and a second current follower configured to operate in response to a voltage or current on a second current determination and/or voltage generation node of the second current determiner, a first transmission gate disposed between the first current determiner and the second current determiner, and a second transmission gate between the first current follower and the second current follower, the conversion unit being configured to provide a first conversion voltage and a second conversion voltage that vary in response to the differential input signal at the input unit;
- an amplification unit configured to provide an output voltage in response to the first conversion voltage and the second conversion voltage;
- a frequency compensation circuit comprising a first compensation capacitor disposed between an output terminal and the first current follower and a second compensation capacitor disposed between the output terminal and the second current follower;
- and
- a short-circuit current minimization circuit comprising a first short-circuit compensation capacitor disposed between the output terminal and the first current determination and/or voltage generation node and a second short-circuit compensation capacitor disposed between the output terminal and the second current determination and/or voltage generation node.
3 more elements
An amplifier comprising:
- an input unit configured to receive a differential input signal at a first input terminal and a second input terminal;
- a conversion unit comprising a first current mirror comprising a first current determiner and a first current follower configured to operate in response to a voltage or current on a first current determination and/or voltage generation node of the first current determiner, a second current mirror comprising a second current determiner and a second current follower configured to operate in response to a voltage or current on a second current determination and/or voltage generation node of the second current determiner, a first transmission gate disposed between the first current determiner and the second current determiner, and a second transmission gate between the first current follower and the second current follower, the conversion unit being configured to provide a first conversion voltage and a second conversion voltage that vary in response to the differential input signal at the input unit;
- an amplification unit configured to provide an output voltage in response to the first conversion voltage and the second conversion voltage;
- a frequency compensation circuit comprising a first compensation capacitor disposed between an output terminal and the first current follower and a second compensation capacitor disposed between the output terminal and the second current follower;
- a short-circuit current minimization circuit comprising a first short-circuit compensation capacitor disposed between the output terminal and the first current determination and/or voltage generation node and a second short-circuit compensation capacitor disposed between the output terminal and the second current determination and/or voltage generation node;
- and
- a slew rate improvement circuit configured to reversibly connect an output terminal of the amplification unit and an input terminal of the amplification unit in response to a voltage at the first input terminal.
4 more elements
Dependencies are inferred from the claim text.